PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet
PIC18F2455-I/SP
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PIC18F2455-I/SP Summary of contents
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... High-Performance, © 2006 Microchip Technology Inc. PIC18F2450/4450 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology Advance Information Data Sheet DS39760A ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Advance Information , microID, MPLAB, PIC, PICmicro, PICSTART, ® 8-bit MCUs ® code hopping EE OQ © 2006 Microchip Technology Inc. ...
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... PIC18F4450 16K 8192 * Includes 256 bytes of dual access RAM used by USB module and shared with data memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 Peripheral Highlights: • High-current sink/source: 25 mA/25 mA • Three external interrupts • Three Timer modules (Timer0 to Timer2) • Capture/Compare/PWM (CCP) module: - Capture is 16-bit, max ...
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... RA5/AN4/HLVDIN V OSC1/CLKI OSC2/CLKO/RA6 Note: Pinouts are subject to change. DS39760A-page 2 /RE3 REF REF USB RB3/AN9/VPO + 2 20 RB2/AN8/INT2/VMO 3 19 RB1/AN10/INT1 PIC18F2450 4 18 RB0/AN12/INT0 RC7/RX/ Advance Information RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/VPO RB2/AN8/INT2/VMO RB1/AN10/INT1 RB0/AN12/INT0 RC7/RX/DT RC6/TX/CK RC5/D+/VP RC4/D-/ © 2006 Microchip Technology Inc. ...
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... RE2/AN7 V V OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/UOE RC2/CCP1 V USB RD0 RD1 44-Pin QFN RC7/RX/DT RD4 RD5 RD6 RD7 RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO Note: Pinouts are subject to change. © 2006 Microchip Technology Inc. PIC18F2450/4450 1 RB7/KBI3/PGD 40 RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 37 + RB3/AN9/VPO 5 36 RB2/AN8/INT2/VMO RB1/AN10/INT1 34 8 RB0/AN12/INT0 ...
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... V DD RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO Note: Pinouts are subject to change. * Assignment of this feature is dependent on device configuration. DS39760A-page 4 NC/ICRST*/ICV 1 33 RC0/T1OSO/T1CKI 2 32 OSC2/CLKO/RA6 31 3 OSC1/CLKI PIC18F4450 RE2/AN7 27 7 RE1/AN6 8 26 RE0/AN5 9 25 RA5/AN4/HLVDIN RA4/T0CKI/RCV 11 Advance Information * © 2006 Microchip Technology Inc. ...
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... Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 305 Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 305 Index ................................................................................................................................................................................................. 307 The Microchip Web Site ..................................................................................................................................................................... 315 Customer Change Notification Service .............................................................................................................................................. 315 Customer Support .............................................................................................................................................................................. 315 Reader Response .............................................................................................................................................................................. 316 PIC18F2450/4450 Product Identification System .............................................................................................................................. 317 © 2006 Microchip Technology Inc. PIC18F2450/4450 Advance Information DS39760A-page 5 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39760A-page 6 Advance Information © 2006 Microchip Technology Inc. ...
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... Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. It also incorporates its own on-chip transceiver and 3.3V regulator and supports the use of external transceivers and voltage regulators. © 2006 Microchip Technology Inc. PIC18F2450/4450 1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES ...
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... Standard devices with Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2450), accommodate an operating V range of 4.2V to 5.5V. Low-voltage parts, DD designated by “LF” (such as PIC18LF2450), function over an extended V Advance Information range of 2.0V to 5.5V. DD © 2006 Microchip Technology Inc. ...
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... Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced USART Universal Serial Bus (USB) Module 10-bit Analog-to-Digital Module Resets (and Delays) Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set Packages © 2006 Microchip Technology Inc. PIC18F2450/4450 PIC18F2450 DC – 48 MHz 16384 8192 768 13 Ports ( ...
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... Timer2 10-bit EUSART Advance Information PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI/RCV RA5/AN4/HLVDIN OSC2/CLKO/RA6 PORTB RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2/VMO RB3/AN9/VPO RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI 8 RC1/T1OSI/UOE RC2/CCP1 RC4/D-/VM RC5/D+/VP RC6/TX/CK RC7/RX/DT 8 PORTE (1) MCLR/V /RE3 PP USB © 2006 Microchip Technology Inc. ...
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... Section 2.0 “Oscillator Configurations” for additional information. 3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated Packages Only)” for additional information. © 2006 Microchip Technology Inc. PIC18F2450/4450 Data Bus<8> Data Latch ...
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... Crystal Oscillator mode. O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2006 Microchip Technology Inc. ...
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... RA5 AN4 HLVDIN RA6 — — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0. ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2006 Microchip Technology Inc. ...
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... USB Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — Timer1 oscillator output Timer1external clock input. I/O ST Digital I/O ...
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... Crystal Oscillator mode. O — In select modes, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2006 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels O = Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2006 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels O = Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... PORTD is a bidirectional I/O port. 38 I/O ST Digital I/O. 39 I/O ST Digital I/O. 40 I/O ST Digital I/O. 41 I/O ST Digital I/O. 2 I/O ST Digital I/O. 3 I/O ST Digital I/O. 4 I/O ST Digital I/O. 5 I/O ST Digital I/O. CMOS = CMOS compatible input or output I = Input P = Power Advance Information Description © 2006 Microchip Technology Inc. ...
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... Schmitt Trigger input with CMOS levels O = Output Note 1: These pins are No Connect unless the ICPRT Configuration bit is set. For NC/ICPORTS, the pin is No Connect unless ICPRT is set and the DEBUG Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... PIC18F2450/4450 NOTES: DS39760A-page 22 Advance Information © 2006 Microchip Technology Inc. ...
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... The OSCCON register (Register 2-1) selects the Active Clock mode primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 2.4.1 “Oscillator Control Register”. © 2006 Microchip Technology Inc. PIC18F2450/4450 2.2 Oscillator Types PIC18F2450/4450 devices can be operated in twelve distinct oscillator modes. In contrast with the non-USB PIC18 enhanced microcontrollers, four of these modes involve the use of two oscillator types at once ...
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... Advance Information USB Clock Source USBDIV 0 1 FSEN 1 USB Peripheral 0 4 CPU 1 0 Primary Clock IDLEN Peripherals T1OSC Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up © 2006 Microchip Technology Inc. ...
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... DD See the notes following Table 2-2 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2006 Microchip Technology Inc. PIC18F2450/4450 TABLE 2-2: Osc Type XT HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... MHz which drives the PLL directly. FIGURE 2-6: HS/EC/ECIO/XT Oscillator Enable (from CONFIG1H Register) OSC2 Oscillator and OSC1 Prescaler Advance Information PLL BLOCK DIAGRAM (HS MODE) PLL Enable Phase Comparator OUT Loop Filter VCO 24 SYSCLK © 2006 Microchip Technology Inc. ...
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... OSC1/CLKI; the OSC2/ CLKO pin functions as a digital I/O (RA6). Of these four modes, only INTIO mode frees up an additional pin (OSC2/CLKO/RA6) for port I/O use. © 2006 Microchip Technology Inc. PIC18F2450/4450 2.3 Oscillator Settings for USB When the PIC18F2450/4450 is used for USB ...
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... MHz 40 MHz 20 MHz 13.33 MHz 10 MHz 48 MHz 32 MHz 24 MHz 16 MHz 24 MHz 12 MHz 8 MHz 6 MHz 48 MHz 32 MHz 24 MHz 16 MHz 20 MHz 10 MHz 6.67 MHz 5 MHz 48 MHz 32 MHz 24 MHz 16 MHz 16 MHz 8 MHz 5.33 MHz 4 MHz 48 MHz 32 MHz 24 MHz 16 MHz © 2006 Microchip Technology Inc. ...
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... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid when the USBDIV Configuration bit is cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Clock Mode MCU Clock Division (FOSC3:FOSC0) ...
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... This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. Advance Information © 2006 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 1-0 SCS1:SCS0: System Clock Select bits 1x = Internal oscillator 01 = Timer1 oscillator 00 = Primary oscillator Note 1: Depends on the state of the IESO Configuration bit. © 2006 Microchip Technology Inc. PIC18F2450/4450 (1) U-0 R U-0 — OSTS — Unimplemented bit, read as ‘0’ ...
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... OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level Advance Information (parameter 38, CSD OSC2 Pin © 2006 Microchip Technology Inc. ...
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... RC_IDLE 1 1x Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Clock is INTRC source. © 2006 Microchip Technology Inc. PIC18F2450/4450 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: power • The primary clock, as defined by the FOSC3:FOSC0 Configuration bits • ...
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... OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run n-1 n (1) Clock Transition OSC Advance Information oscillator has started. In such © 2006 Microchip Technology Inc. ...
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... PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur dur- ing entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator, the use of RC_RUN mode is not recommended. © 2006 Microchip Technology Inc. PIC18F2450/4450 ...
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... OST OSC PLL 2: Clock transition typically occurs within 2-4 T DS39760A-page n-1 n (1) Clock Transition OSC (1) T PLL 1 2 n-1 n (2) Clock Transition OSTS bit Set = 2 ms (approx). These intervals are not shown to scale. . OSC Advance Information © 2006 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2006 Microchip Technology Inc. PIC18F2450/4450 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet run- ning, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD PC Advance Information © 2006 Microchip Technology Inc. ...
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... Section 8.0 “Interrupts”). © 2006 Microchip Technology Inc. PIC18F2450/4450 A fixed delay of interval T is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay ...
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... CSD (1) INTRC None OST (3) XT XTPLL, HSPLL T OST CSD ( (1) INTRC T IOBST . PLL (parameter 39, Table 21-10), the INTRC stabilization period. IOBST Advance Information Clock Ready Status Bit (OSCCON) OSTS ( OSTS (2) ( OSTS (2) ( OSTS (4) is the PLL lock time-out rc © 2006 Microchip Technology Inc. ...
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... Ripple Counter Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2006 Microchip Technology Inc. PIC18F2450/4450 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after POR). DS39760A-page 42 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Advance Information (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... The state of the bit is set to ‘0’ whenever a POR occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. © 2006 Microchip Technology Inc. PIC18F2450/4450 FIGURE 4- ...
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... BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. Advance Information © 2006 Microchip Technology Inc. ...
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... Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2006 Microchip Technology Inc. PIC18F2450/4450 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly differ- ent from other oscillator modes ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39760A-page 46 T PWRT T OST T PWRT T PWRT Advance Information , V RISE < PWRT ): CASE OST ): CASE OST © 2006 Microchip Technology Inc. ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the Power-up Timer. PLL © 2006 Microchip Technology Inc. PIC18F2450/4450 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( Advance Information STKPTR Register POR BOR STKFUL STKUNF © 2006 Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-3 for Reset value for specific condition. 5: PORTA<6>, LATA<6> and TRISA<6> are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 MCLR Resets, Power-on Reset, ...
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... Advance Information Wake-up via WDT or Interrupt ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu uu-u uuuu -uuu uuuu -uuu uuu- -uuu uuu- u--u uuuu u--u uuuu -uuu uuuu -uuu uuuu ---- -uuu uuuu uuuu © 2006 Microchip Technology Inc. ...
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... Program Memory”. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2450/4450 DEVICES CALL, RCALL, RETURN, RETFIE, RETLW, CALLW, ADDULNK, SUBULNK © 2006 Microchip Technology Inc. PIC18F2450/4450 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 Advance Information Stack Pointer STKPTR<4:0> 00010 © 2006 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2006 Microchip Technology Inc. PIC18F2450/4450 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. Advance Information COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh © 2006 Microchip Technology Inc. ...
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... Note: All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2006 Microchip Technology Inc. PIC18F2450/4450 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Advance Information address embedded into the Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2006 Microchip Technology Inc. ...
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... Additional information on USB RAM and buffer operation is provided in Section 14.0 “Universal Serial Bus (USB)”. © 2006 Microchip Technology Inc. PIC18F2450/4450 5.3.2 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2006 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, © 2006 Microchip Technology Inc. PIC18F2450/4450 Data Memory 000h ...
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... UEIE LATB F6Ah UEIR LATA F69h UIE (2) — F68h UIR (2) — F67h UFRMH (2) — F66h UFRML (2) (2) — F65h — (2) PORTE F64h — (3) (2) PORTD F63h — (2) PORTC F62h — (2) PORTB F61h — (2) PORTA F60h — © 2006 Microchip Technology Inc. ...
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... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 4 Bit 3 Bit 2 — ...
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... LATE1 LATE0 51, 110 ---- -xxx LATD1 LATD0 51, 108 xxxx xxxx LATC1 LATC0 51, 106 xx-- -xxx LATB1 LATB0 51, 103 xxxx xxxx LATA1 LATA0 51, 100 -xxx xxxx (3) (3) RE1 RE0 51, 109 ---- x000 RD1 RD0 51, 108 xxxx xxxx © 2006 Microchip Technology Inc. ...
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... RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’. 6: RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0). © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 4 Bit 3 Bit 2 ...
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... Table 19-2 and Table 19-3. Note: The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information R/W-x R/W-x (1) ( bit Bit is unknown © 2006 Microchip Technology Inc. ...
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... Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 5.3.4 “General © 2006 Microchip Technology Inc. PIC18F2450/4450 Purpose Register File” location in the Access Bank (Section 5.3.3 “Access Bank”) as the data source for the instruction. The Access RAM bit ‘ ...
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... BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L Advance Information 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 E00h Bank 14 Bank 14 F00h Bank 15 FFFh Data Memory © 2006 Microchip Technology Inc. ...
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... In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 5.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases ...
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... Figure 5-8. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 19.2.1 “Extended Instruction Syntax”. Advance Information © 2006 Microchip Technology Inc. ...
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... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. © 2006 Microchip Technology Inc. PIC18F2450/4450 000h 060h 080h Bank 0 100h Bank 1 ...
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... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Advance Information 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank © 2006 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F2450/4450 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset or a write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Advance Information Table Latch (8-bit) TABLAT © 2006 Microchip Technology Inc. ...
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... The WR bit can only be set (not cleared) in software Write cycle complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the CFGS bit is not cleared. This allows tracing of the error condition. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-x R/W-0 (1) FREE ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE ERASE TABLE READ – TBLPTR<21:0> Advance Information TBLPTRL 0 © 2006 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2006 Microchip Technology Inc. PIC18F2450/4450 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Advance Information © 2006 Microchip Technology Inc. ...
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... WREN to enable byte writes. 8. Disable interrupts. 9. Write 55h to EECON2. © 2006 Microchip Technology Inc. PIC18F2450/4450 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. ...
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... TBLWT holding register. ; loop until buffers are full Advance Information © 2006 Microchip Technology Inc. ...
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... USBIF PIE2 OSCFIE — USBIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash access. © 2006 Microchip Technology Inc. PIC18F2450/4450 ; access Flash program memory ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ...
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... PIC18F2450/4450 NOTES: DS39760A-page 82 Advance Information © 2006 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 7-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 7-2: MOVF ARG1, W MULWF ARG2 ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2006 Microchip Technology Inc. ...
Page 87
... INTCON<7> is the GIE bit which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. © 2006 Microchip Technology Inc. PIC18F2450/4450 When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit ...
Page 88
... INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Advance Information Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL GIE/GIEH © 2006 Microchip Technology Inc. ...
Page 89
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2006 Microchip Technology Inc. PIC18F2450/4450 Note: Interrupt flag bits are set when an interrupt ...
Page 90
... This feature allows for software polling. DS39760A-page 88 R/W-1 U-0 R/W-1 — INTEDG2 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information U-0 R/W-1 — RBIP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 91
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 ...
Page 92
... R-0 U-0 R/W-0 TXIF — CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information software should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 2 HLVDIF: High/Low-Voltage Detect Interrupt Flag bit high/low-voltage condition occurred high/low-voltage event has occurred bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIF U = Unimplemented bit, read as ‘0’ ...
Page 94
... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS39760A-page 92 R/W-0 U-0 R/W-0 TXIE — CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 95
... Disabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-0 — — HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 96
... TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39760A-page 94 R/W-1 U-0 R/W-1 TXIP — CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 97
... Low priority bit 4-3 Unimplemented: Read as ‘0’ bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/W-1 — — HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 98
... The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. DS39760A-page 96 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) Advance Information (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 99
... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2006 Microchip Technology Inc. PIC18F2450/4450 8.8 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
Page 100
... PIC18F2450/4450 NOTES: DS39760A-page 98 Advance Information © 2006 Microchip Technology Inc. ...
Page 101
... Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). © 2006 Microchip Technology Inc. PIC18F2450/4450 Reading the PORTA register reads the status of the pins; writing to it will write to the port latch. ...
Page 102
... LATA2 TRISA5 TRISA4 TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 SE0 PKTDIS USBEN RESUME SUSPND Advance Information Description /4); available in EC, ECPLL and OSC Reset Bit 1 Bit 0 Values on page RA1 RA0 51 LATA1 LATA0 51 TRISA1 TRISA0 51 PCFG1 PCFG0 50 — 52 © 2006 Microchip Technology Inc. ...
Page 103
... MOVFF (ANY), PORTB instruction). This will end the mismatch condition. b) Clear flag bit, RBIF. © 2006 Microchip Technology Inc. PIC18F2450/4450 A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF cleared. ...
Page 104
... PORTB<7> data input; weak pull-up when RBPU bit is cleared. IN TTL Interrupt-on-pin change. DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Advance Information Description (1) (1) (1) (1) (1) (2) (2) (2) © 2006 Microchip Technology Inc. ...
Page 105
... RBPU INTEDG0 INTEDG1 INTEDG2 INTCON3 INT2IP INT1IP ADCON1 — — UCON — PPBRST Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB. © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
Page 106
... CLRF PORTC CLRF LATC MOVLW 07h MOVWF TRISC Advance Information transceiver must be disabled INITIALIZING PORTC ; Initialize PORTC by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; RC<5:0> as outputs ; RC<7:6> as inputs © 2006 Microchip Technology Inc. ...
Page 107
... TTL = TTL Buffer Input, XCVR = USB Transceiver Don’t care (TRIS bit does not affect port direction or is overridden for this option) Note 1: RC4 and RC5 do not have corresponding TRISC bits. In Port mode, these pins are input only. USB data direction is determined by the USB configuration. © 2006 Microchip Technology Inc. PIC18F2450/4450 I/O I/O Type OUT DIG LATC< ...
Page 108
... Bit 5 Bit 4 Bit 3 Bit 2 (1) (1) RC5 RC4 — RC2 — — — LATC2 — — — TRISC2 SE0 PKTDIS USBEN RESUME SUSPND Advance Information Reset Bit 1 Bit 0 Values on page RC1 RC0 51 LATC1 LATC0 51 TRISC1 TRISC0 51 — 52 © 2006 Microchip Technology Inc. ...
Page 109
... PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note Power-on Reset, these pins are configured as digital inputs. © 2006 Microchip Technology Inc. PIC18F2450/4450 EXAMPLE 9-4: CLRF PORTD CLRF LATD MOVLW ...
Page 110
... LATD<7> data output PORTD<7> data input. Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 LATD5 LATD4 LATD3 LATD2 TRISD5 TRISD4 TRISD3 TRISD2 Advance Information Description Reset Bit 1 Bit 0 Values on page RD1 RD0 51 LATD1 LATD0 51 TRISD1 TRISD0 51 © 2006 Microchip Technology Inc. ...
Page 111
... RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices). 3: Unimplemented in 28-pin devices; read as ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. ...
Page 112
... Bit 3 Bit 2 (1,2) — — RE3 RE2 — — — LATE2 — — — TRISE2 VCFG1 VCFG0 PCFG3 PCFG2 Advance Information Description Reset Bit 1 Bit 0 Values on page (3) (3) (3) RE1 RE0 51 LATE1 LATE0 51 TRISE1 TRISE0 51 PCFG1 PCFG0 50 © 2006 Microchip Technology Inc. ...
Page 113
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2006 Microchip Technology Inc. PIC18F2450/4450 The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-Bit mode is shown in Figure 10-1 ...
Page 114
... Sync with Internal TMR0L Clocks Delay Advance Information ). There is a delay between OSC Set TMR0IF TMR0L on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...
Page 115
... Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 10.3.1 SWITCHING PRESCALER ...
Page 116
... PIC18F2450/4450 NOTES: DS39760A-page 114 Advance Information © 2006 Microchip Technology Inc. ...
Page 117
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2006 Microchip Technology Inc. PIC18F2450/4450 A simplified block diagram of the Timer1 module is shown in Figure 11-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 11-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 118
... Special Event Trigger) 8 Advance Information 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2006 Microchip Technology Inc. ...
Page 119
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 11-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F2450/4450 TABLE 11-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 120
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. Advance Information a Special Event Trigger © 2006 Microchip Technology Inc. ...
Page 121
... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. © 2006 Microchip Technology Inc. PIC18F2450/4450 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ...
Page 122
... PIC18F2450/4450 NOTES: DS39760A-page 120 Advance Information © 2006 Microchip Technology Inc. ...
Page 123
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2006 Microchip Technology Inc. PIC18F2450/4450 12.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by- 16 prescale options. These are selected by the prescaler control bits, T2CKPS1:T2CKPS0 (T2CON< ...
Page 124
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF — CCP1IF TXIE — CCP1IE TXIP — CCP1IP Advance Information Set TMR2IF TMR2 Output (to PWM) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP © 2006 Microchip Technology Inc. ...
Page 125
... Compare mode: generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin reflects I/O state) 1011 = Compare mode: trigger special event, reset timer and start A/D conversion on CCP1 match (CCP1IF bit is set) 11xx = PWM mode © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R/W-0 ...
Page 126
... Edge Detect 4 4 Advance Information CHANGING BETWEEN CAPTURE PRESCALERS (CCP1 SHOWN) ; Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP1CON with ; this value CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L © 2006 Microchip Technology Inc. ...
Page 127
... COMPARE MODE OPERATION BLOCK DIAGRAM CCPR1H CCPR1L Compare Comparator TMR1H TMR1L © 2006 Microchip Technology Inc. PIC18F2450/4450 13.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP1M3:CCP1M0 = 1010), the CCP1 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP1IE bit is set. ...
Page 128
... TRISC2 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 Advance Information Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 TRISC1 TRISC0 TMR1CS TMR1ON © 2006 Microchip Technology Inc. ...
Page 129
... FIGURE 13-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 © 2006 Microchip Technology Inc. PIC18F2450/4450 13.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: EQUATION 13-1: PWM Period = [(PR2 • ...
Page 130
... CCP1M3 CCP1M2 Advance Information 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 Reset Bit 2 Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 TRISC1 TRISC0 CCP1M1 CCP1M0 50 © 2006 Microchip Technology Inc. ...
Page 131
... Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1). 2: The pull-ups can be supplied either from the not enable the internal regulator when using an external 3.3V supply. © 2006 Microchip Technology Inc. PIC18F2450/4450 any USB host and the PIC be interfaced directly to the USB, utilizing the internal transceiver can be connected through an external transceiver ...
Page 132
... R/C-0 R/W-0 R/W-0 PKTDIS USBEN RESUME U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 U-0 SUSPND — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 133
... These include: • Bus Speed (full speed versus low speed) • On-Chip Transceiver Enable • Ping-Pong Buffer Usage © 2006 Microchip Technology Inc. PIC18F2450/4450 The UCFG register also contains two bits which aid in module testing, debugging and USB certifications. These bits control output enable state monitoring and eye pattern generation ...
Page 134
... SIE that can’t be captured with the RCV signal. The combinations of states of these signals and their interpretation are listed in Table 14-1 and Table 14-2. Advance Information R/W-0 R/W-0 (2) PPB1 PPB0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 135
... Ping-Pong Buffer Configuration The usage of ping-pong buffers is configured using the PPB1:PPB0 bits. Refer to Section 14.4.4 “Ping-Pong Buffering” for a complete explanation of the ping-pong buffers. © 2006 Microchip Technology Inc. PIC18F2450/4450 14.2.2.5 USB Output Enable Monitor The USB OE monitor provides indication as to whether the SIE is listening to the bus or actively driving the bus ...
Page 136
... Data Bus R-x R-x R-x ENDP1 ENDP0 DIR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information FIFO is full, the SIE will USTAT FIFO Clearing TRNIF Advances FIFO R-x U-0 (1) PPBI — bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 137
... EPSTALL: Endpoint Stall Enable bit 1 = Endpoint n is stalled 0 = Endpoint n is not stalled Note 1: Valid only if Endpoint n is enabled; otherwise, the bit is ignored. © 2006 Microchip Technology Inc. PIC18F2450/4450 transactions. For Endpoint 0, this bit should always be cleared since the Endpoint 0 as the default control endpoint. ...
Page 138
... Advance Information IMPLEMENTATION OF USB RAM IN DATA MEMORY SPACE 000h User Data 1FFh 200h Unused Unused 3FFh 400h Buffer Descriptors, USB Data or User Data 4FFh 500h USB Data or User Data 7FFh 800h Unused F00h F80h SFRs FFFh © 2006 Microchip Technology Inc. ...
Page 139
... UEPn register. All BD registers are available in USB RAM. The BD for each endpoint should be set up prior to enabling the endpoint. © 2006 Microchip Technology Inc. PIC18F2450/4450 14.4.1 BD STATUS AND CONFIGURATION Buffer descriptors not only define the size of an endpoint buffer, but also determine its configuration and control ...
Page 140
... Device Response after Receiving Packet DTS Handshake UOWN TRNIF ACK ACK ACK ACK ACK NAK Advance Information “BD Byte Count” for more BDnSTAT and USTAT Status Updated Not Updated Updated Not Updated Updated Not Updated © 2006 Microchip Technology Inc. ...
Page 141
... This bit must be initialized by the user to the desired value prior to enabling the USB module. 2: This bit is ignored unless DTSEN = these bits are set, USB communication may not work. Hence, these bits should always be maintained as ‘0’. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-x R/W-x (3) — ...
Page 142
... R/W-x R/W-x R/W-x PID2 PID1 PID0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information When developing USB R/W-x R/W-x BC9 BC8 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 143
... Maximum Memory Used: 128 bytes Maximum BDs: 32 (BD0 to BD31) Note: Memory area not shown to scale. © 2006 Microchip Technology Inc. PIC18F2450/4450 SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. ...
Page 144
... Bit 2 Bit 1 Bit 0 (2) PID0 BC9 BC8 (3) BSTALL © 2006 Microchip Technology Inc. ...
Page 145
... The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers will spread across multiple frames. © 2006 Microchip Technology Inc. PIC18F2450/4450 Figure 14-8 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts ...
Page 146
... R/W-0 R/W-0 R/W-0 (1) (2) IDLEIF TRNIF ACTVIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) (3) (4) Advance Information R-0 R/W-0 (3) (4) UERRIF URSTIF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 147
... URSTIE: USB Reset Interrupt Enable bit 1 = USB Reset interrupt enabled 0 = USB Reset interrupt disabled © 2006 Microchip Technology Inc. PIC18F2450/4450 The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt ...
Page 148
... Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. R/C-0 R/C-0 R/C-0 BTOEF DFN8EF CRC16EF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/C-0 R/C-0 CRC5EF PIDEF bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 149
... CRC5 host error interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = PID check failure interrupt enabled 0 = PID check failure interrupt disabled © 2006 Microchip Technology Inc. PIC18F2450/4450 As with the UIE register, the enable bits only affect the propagation of microcontroller’s interrupt logic. The flag bits are still ...
Page 150
... USB Firmware and Drivers USB Microchip provides a number of application-specific SS resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support. Advance Information DUAL POWER EXAMPLE 100 k Attach Sense I/O pin USB V SS © 2006 Microchip Technology Inc. ...
Page 151
... This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 14-5. © 2006 Microchip Technology Inc. PIC18F2450/4450 Bit 5 ...
Page 152
... Devices may either be self-powered or bus powered. Self-powered devices draw power from an external source, while bus powered devices use power supplied from the bus. Device To other Configurations (if any) Configuration Interface Endpoint Endpoint Endpoint Advance Information To other Interfaces (if any) © 2006 Microchip Technology Inc. ...
Page 153
... Device Descriptor The device descriptor provides general information, such as manufacturer, product number, serial number, the class of the device and the number of configurations. There is only one device descriptor. © 2006 Microchip Technology Inc. PIC18F2450/4450 14.9.6.2 Configuration Descriptor The configuration descriptor provides information on ...
Page 154
... PIC18F2450/4450 NOTES: DS39760A-page 152 Advance Information © 2006 Microchip Technology Inc. ...
Page 155
... Break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity © 2006 Microchip Technology Inc. PIC18F2450/4450 The pins of the Enhanced USART are multiplexed with PORTC. In order to configure RC6/TX/CK and RC7/RX EUSART: • ...
Page 156
... SREN/CREN overrides TXEN in Sync mode with the exception that SREN has no effect in Synchronous Slave mode. DS39760A-page 154 R/W-0 R/W-0 R/W-0 (1) SYNC SENDB BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Advance Information R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 157
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R-0 CREN ...
Page 158
... Baud rate measurement disabled or completed Synchronous mode: Unused in this mode. DS39760A-page 156 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Advance Information R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 159
... SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. © 2006 Microchip Technology Inc. PIC18F2450/4450 the high baud rate (BRGH = 1) or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency ...
Page 160
... SPBRG Actual SPBRG % % value Rate value Error (decimal) (K) (decimal) — — — — — — — — 255 2403 -0.16 207 64 9615 -0. 19230 -0. 55555 3. — — — SPBRG % value (decimal) 207 51 25 — — — — © 2006 Microchip Technology Inc. ...
Page 161
... Microchip Technology Inc. PIC18F2450/4450 SYNC = 0, BRGH = 0, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (decimal) (K) 0.300 ...
Page 162
... TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation. Advance Information using the Auto-Baud Rate BRG Counter Clock F /512 OSC F /128 OSC F /128 OSC F /32 OSC © 2006 Microchip Technology Inc. ...
Page 163
... Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0. FIGURE 15-2: BRG OVERFLOW SEQUENCE BRG Clock ABDEN bit RX pin ABDOVF bit BRG Value XXXXh © 2006 Microchip Technology Inc. PIC18F2450/4450 Edge #1 Edge #2 Edge #3 bit 3 Start bit 1 bit 0 ...
Page 164
... If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Data Bus TXREG Register 8 MSb LSb (8) 0 TSR Register TRMT TX9 TX9D Advance Information ), the TXREG register is empty CY Pin Buffer and Control TX pin SPEN © 2006 Microchip Technology Inc. ...
Page 165
... SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 bit 0 bit 1 Word 1 bit 0 ...
Page 166
... ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. CREN OERR 64 MSb or 16 Stop ( RX9 Data Recovery RX9D Interrupt RCIF RCIE Advance Information FERR RSR Register LSb Start 1 0 RCREG Register FIFO 8 Data Bus © 2006 Microchip Technology Inc. ...
Page 167
... SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. © 2006 Microchip Technology Inc. PIC18F2450/4450 Start bit 0 bit 7/8 ...
Page 168
... If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Cleared due to user read of RCREG Cleared due to user read of RCREG Sleep Ends Advance Information Auto-Cleared Auto-Cleared Note 1 © 2006 Microchip Technology Inc. ...
Page 169
... TRMT bit (Transmit Shift Reg. Empty Flag) SENDB sampled here SENDB (Transmit Shift Reg. Empty Flag) © 2006 Microchip Technology Inc. PIC18F2450/4450 3. Load the TXREG with a dummy character to initiate transmission (the value is ignored). 4. Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer ...
Page 170
... Start transmission by loading data to the TXREG register using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set Q1Q2 bit 1 bit 2 bit 7 bit 0 Word 1 Advance Information ), the TXREG register is CYCLE bit 1 bit 7 Word 2 ‘1’ © 2006 Microchip Technology Inc. ...
Page 171
... SPBRGH EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 bit 0 bit 2 bit 1 Bit 5 ...
Page 172
... ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 Advance Information bit 6 bit 7 ‘0’ Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 — WUE ABDEN © 2006 Microchip Technology Inc. ...
Page 173
... EUSART Baud Rate Generator Register High Byte SPBRG EUSART Baud Rate Generator Register Low Byte Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission. © 2006 Microchip Technology Inc. PIC18F2450/4450 To set up a Synchronous Slave Transmission: 1. ...
Page 174
... CCP1IP SREN CREN ADDEN FERR TXEN SYNC SENDB BRGH — SCKP BRG16 — Advance Information Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP 51 OERR RX9D 51 50 TRMT TX9D 51 WUE ABDEN © 2006 Microchip Technology Inc. ...
Page 175
... Note 1: These channels are not implemented on 28-pin devices. 2: Performing a conversion on unimplemented channels will return a floating input measurement. © 2006 Microchip Technology Inc. PIC18F2450/4450 The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins ...
Page 176
... AN5 through AN7 are available only on 40/44-pin devices. DS39760A-page 174 (1) R/W-0 R/W-0 R/W VCFG0 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared - source) REF + source) REF Digital I/O Advance Information (1) (1) (1) R/W R/W PCFG1 PCFG0 bit Bit is unknown © 2006 Microchip Technology Inc. ...
Page 177
... F /2 OSC Note 1: If the A/D F clock source is selected, a delay of one T RC clock starts. This allows the SLEEP instruction to be executed before starting a conversion. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/W-0 R/W-0 R/W-0 ACQT1 ACQT0 ADCS2 U = Unimplemented bit, read as ‘0’ ...
Page 178
... AIN (Input Voltage) VCFG1:VCFG0 DD ( REF REF and Advance Information 1100 AN12 1011 AN11 1010 AN10 1001 AN9 1000 AN8 0111 (1) AN7 0110 (1) AN6 0101 (1) AN5 0100 AN4 0011 AN3 0010 AN2 0001 AN1 0000 AN0 © 2006 Microchip Technology Inc. ...
Page 179
... SS = Sampling Switch C = Sample/hold Capacitance (from DAC) HOLD R = Sampling Switch Resistance SS © 2006 Microchip Technology Inc. PIC18F2450/4450 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt 6. Read A/D Result registers (ADRESH:ADRESL); ...
Page 180
... Example 16-3 shows the calculation of the minimum required acquisition time T based on . The sampling assumptions: C HOLD Rs Conversion Error V DD Temperature (- HOLD ln(1/2048) S COFF ) ln(1/2047 Advance Information the minimum acquisition time, . This calculation is ACQ the following application system = 2.5 k 1/2 LSb = (system max ms. © 2006 Microchip Technology Inc. ...
Page 181
... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power devices only. © 2006 Microchip Technology Inc. PIC18F2450/4450 16.3 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
Page 182
... RC 3: The Register 3H configures PORTB pins to reset as analog or digital pins by control- ling how the PCFG0 bits in ADCON1 are reset. Advance Information ) will be converted. OL input will be accurately PBADEN bit in Configuration © 2006 Microchip Technology Inc. ...
Page 183
... Conversion starts Time (Holding capacitor is disconnected) Set GO/DONE bit (Holding capacitor continues acquiring input) © 2006 Microchip Technology Inc. PIC18F2450/4450 After the A/D conversion is completed or aborted wait is required before the next acquisition can be AD started. After this wait, acquisition on the selected channel is automatically started ...
Page 184
... TMR1IP 51 51 — — 51 — — 51 — — GO/DONE ADON 50 PCFG1 PCFG0 50 ADCS1 ADCS0 50 RA1 RA0 51 TRISA1 TRISA0 51 RB1 RB0 51 TRISB1 TRISB0 51 LATB1 LATB0 51 (4) (4) (4) RE1 RE0 51 (4) (4) (4) TRISE1 TRISE0 51 (4) (4) (4) LATE1 LATE0 51 © 2006 Microchip Technology Inc. ...
Page 185
... Minimum setting Note 1: See Table 21-4 in Section 21.0 “Electrical Characteristics” for specifications. © 2006 Microchip Technology Inc. PIC18F2450/4450 The High/Low-Voltage (Register 17-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control which minimizes the current consumption for the device ...
Page 186
... HLVDIN. This gives users flexibility because it allows them to configure the High/Low-Voltage Detect interrupt to occur at any voltage in the valid operating range HLVDL3:HLVDL0 HLVDEN Internal Voltage Reference 1.2V Typical Advance Information the HLVDL3:HLVDL0 bits HLVDCON Register VDIRMAG Set HLVDIF © 2006 Microchip Technology Inc. ...
Page 187
... DD HLVDIF Enable HLVD IRVST Internal Reference is stable © 2006 Microchip Technology Inc. PIC18F2450/4450 Depending on the application, the HLVD module does not need to be operating constantly. To decrease the current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked ...
Page 188
... HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists FIGURE 17- Legend Advance Information ) 1 V HLVD HLVDIF cleared in software V HLVD TYPICAL HIGH/LOW-VOLTAGE DETECT APPLICATION Time = HLVD trip point A = Minimum valid device B operating voltage © 2006 Microchip Technology Inc. ...
Page 189
... IPR2 OSCFIP — Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the HLVD module. © 2006 Microchip Technology Inc. PIC18F2450/4450 17.7 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. ...
Page 190
... PIC18F2450/4450 NOTES: DS39760A-page 188 Advance Information © 2006 Microchip Technology Inc. ...
Page 191
... Section 2.0 “Oscillator Configurations”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. © 2006 Microchip Technology Inc. PIC18F2450/4450 In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F2450/4450 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled) ...
Page 192
... PLLDIV1 PLLDIV0 --00 0000 FOSC1 FOSC0 00-- 0101 --01 1111 WDTEN ---1 1111 — 1--- -01- — STVREN 100- 01-1 CP1 CP0 ---- --11 — — -1-- ---- WRT1 WRT0 ---- --11 — — -11- ---- EBTR1 EBTR0 ---- --11 — — -1-- ---- (1) REV1 REV0 xxxx xxxx (1) DEV4 DEV3 0001 0010 © 2006 Microchip Technology Inc. ...
Page 193
... Divide by 5 (20 MHz oscillator input) 011 = Divide by 4 (16 MHz oscillator input) 010 = Divide by 3 (12 MHz oscillator input) 001 = Divide MHz oscillator input) 000 = No prescale (4 MHz oscillator input drives PLL directly) © 2006 Microchip Technology Inc. PIC18F2450/4450 R/P-0 R/P-0 R/P-1 CPUDIV1 ...
Page 194
... EC modes. The USB module uses the indicated XT oscillator as its clock source whenever the microcontroller uses the internal oscillator. DS39760A-page 192 U-0 R/P-0 R/P-1 (1) — FOSC3 FOSC2 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state (1) Advance Information R/P-1 R/P-1 (1) (1) (1) FOSC1 FOSC0 bit 0 © 2006 Microchip Technology Inc. ...
Page 195
... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: See Section 21.0 “Electrical Characteristics” for the specifications. 2: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. © 2006 Microchip Technology Inc. PIC18F2450/4450 R/P-1 R/P-1 R/P-1 (1) (1) BORV1 ...
Page 196
... WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) DS39760A-page 194 R/P-1 R/P-1 R/P-1 WDTPS3 WDTPS2 WDTPS1 U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information R/P-1 R/P-1 WDTPS0 WDTEN bit 0 © 2006 Microchip Technology Inc. ...
Page 197
... PBADEN: PORTB A/D Enable bit (Affects ADCON1 Reset state. ADCON1 controls PORTB<4:0> pin configuration PORTB<4:0> pins are configured as analog input channels on Reset 0 = PORTB<4:0> pins are configured as digital I/O on Reset bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 R/P-0 — ...
Page 198
... Available only on PIC18F4450 devices in 44-pin TQFP packages. Always leave this bit clear in all other devices. DS39760A-page 196 U-0 R/P-0 R/P-1 (1) — BBSIZ U = Unimplemented bit, read as ‘0’ Unchanged from programmed state Advance Information U-0 R/P-1 LVP — STVREN bit 0 (1) © 2006 Microchip Technology Inc. ...
Page 199
... Unimplemented: Read as ‘0’ bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0007FFh) or (000000-000FFFh) is not code-protected 0 = Boot block (000000-0007FFh) or (000000-000FFFh) is code-protected bit 5-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. PIC18F2450/4450 U-0 U-0 U-0 — — — ...
Page 200
... U = Unimplemented bit, read as ‘0’ Unchanged from programmed state U-0 U-0 (1) — — Unimplemented bit, read as ‘0’ Unchanged from programmed state (1) Advance Information U-0 R/C-1 R/C-1 — WRT1 WRT0 bit 0 U-0 U-0 U-0 — — — bit 0 © 2006 Microchip Technology Inc. ...