PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 166

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18F2450/4450
15.2.2
The receiver block diagram is shown in Figure 15-6.
The data is received on the RX pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter operating at x16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F
in RS-232 systems.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
FIGURE 15-6:
DS39760A-page 164
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
EUSART ASYNCHRONOUS
RECEIVER
RX
BRG16
OSC
. This mode would typically be used
EUSART RECEIVE BLOCK DIAGRAM
SPBRGH
Baud Rate Generator
x64 Baud Rate CLK
and Control
Pin Buffer
SPEN
SPBRG
Advance Information
Recovery
Interrupt
Data
or
or
64
16
4
CREN
15.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
RX9
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCIE and GIE bits are set.
Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREG to determine if the device is being
addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
Stop
MSb
RCIF
RCIE
RX9D
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
(8)
OERR
7
RSR Register
RCREG Register
© 2006 Microchip Technology Inc.
8
Data Bus
1
FERR
0
LSb
Start
FIFO