PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 135

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 14-1:
TABLE 14-2:
The UOE signal toggles the state of the external
transceiver. This line is pulled low by the device to
enable the transmission of data from the SIE to an
external device.
14.2.2.3
The PIC18F2450/4450 devices require an external pull-
up resistor to meet the requirements for low-speed and
full-speed USB. Either an external 3.3V supply or the
V
resistor must be 1.5 k
specifications. Figure 14-3 shows an example with the
V
FIGURE 14-3:
14.2.2.4
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 14.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
© 2006 Microchip Technology Inc.
VPO
USB
USB
VP
0
0
1
1
0
0
1
1
Note:
Microcontroller
pin.
pin may be used to pull up D+ or D-. The pull-up
VMO
PIC
VM
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
0
1
0
1
0
1
0
1
®
Pull-up Resistors
Ping-Pong Buffer Configuration
V
USB
D+
D-
DIFFERENTIAL OUTPUTS TO
TRANSCEIVER
SINGLE-ENDED INPUTS
FROM TRANSCEIVER
EXTERNAL CIRCUITRY
(±5%) as required by the USB
Single-Ended Zero
Single-Ended Zero
1.5 k
Illegal Condition
Differential ‘0’
Differential ‘1’
High Speed
Low Speed
Bus State
Bus State
Error
Controller/HUB
Host
Advance Information
14.2.2.5
The USB OE monitor provides indication as to whether
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
transceiver or when UCFG<6> = 1.
The USB OE monitoring is useful for initial system
debugging, as well as scope triggering during eye
pattern generation tests.
14.2.2.6
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB
certification tests. It is intended to show a system
developer the noise integrity of the USB signals which
can be affected by board traces, impedance
mismatches
components. It does not properly test the transition
from a receive to a transmit state. Although the eye
pattern is not meant to replace the more complex USB
certification test, it should aid during first order system
debugging.
14.2.2.7
The PIC18F2450/4450 devices have a built-in 3.3V
regulator to provide power to the internal transceiver and
provide a source for the external pull-ups. An external
220 nF (±20%) capacitor is required for stability.
The regulator is enabled by default and can be disabled
through the VREGEN Configuration bit. When enabled,
the voltage is visible on pin V
is disabled, a 3.3V source must be provided through
the V
transceiver is disabled, V
Note:
Note 1: Do not enable the internal regulator if an
USB
2: V
PIC18F2450/4450
pin for the internal transceiver. If the internal
The drive from V
drive an external pull-up in addition to the
internal transceiver.
external regulator is connected to V
times, even with the regulator disabled.
USB Output Enable Monitor
Eye Pattern Test Enable
Internal Regulator
DD
and
must be greater than V
proximity
USB
USB
is not used.
USB
. When the regulator
to
is sufficient to only
DS39760A-page 133
other
USB
system
USB
at all
.