PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 37

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
(INTRC), there are no distinguishable differences
between the PRI_RUN and RC_RUN modes during
execution. However, a clock switch delay will occur dur-
ing entry to and exit from RC_RUN mode. Therefore, if
the primary clock source is the internal oscillator, the
use of RC_RUN mode is not recommended.
© 2006 Microchip Technology Inc.
Note 1:
CPU Clock
RC_RUN MODE
Peripheral
PLL Clock
Program
Counter
Output
T1OSI
OSC1
Clock
2:
SCS1:SCS0 bits Changed
T
Clock transition typically occurs within 2-4 T
OST
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
= 1024 T
OSC
Q1
; T
T
PLL
OST (1)
= 2 ms (approx). These intervals are not shown to scale.
PC
Q2
Advance Information
T
PLL (1)
OSTS bit Set
Q3
OSC
Q4
.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTRC (see Figure 3-3), the primary oscillator is
shut down and the OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 3-4). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
Q1
1
Transition
2
Clock
(2)
PIC18F2450/4450
n-1 n
PC + 2
Q2
Q3 Q4
Q1
PC + 4
Q2
DS39760A-page 35
Q3