PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 43

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F2455-I/SP

• A/d Inputs: 10-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 12 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 23
• Interface: I2C/SPI/USART/USB
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 24K Bytes
• Ram Size: 2K Bytes
• Speed: 48 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.0
The PIC18F2450/4450 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 18.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
© 2006 Microchip Technology Inc.
Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin.
OSC1
MCLR
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
2: See Table 4-2 for time-out situations.
RESET
INTRC
OST/PWRT
Pointer
32 s
Stack
( )_IDLE
Brown-out
Time-out
V
(1)
Detect
DD
WDT
Reset
Sleep
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
RESET Instruction
Stack Full/Underflow Reset
External Reset
10-bit Ripple Counter
11-bit Ripple Counter
POR Pulse
BOREN
MCLRE
1024 Cycles
65.5 ms
Advance Information
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 8.0
Section 4.4 “Brown-out Reset (BOR)”.
RCON Register
PIC18F2450/4450
“Interrupts”.
S
R
BOR
DS39760A-page 41
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(2)
in