PIC16F1826-I/ML Microchip Technology Inc., PIC16F1826-I/ML Datasheet - Page 117

• Manufacturer Part Number: PIC16F1826-I/ML
• Description: 28 QFN 6x6mm TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/ML

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

12.0
Depending on the device selected and peripherals
enabled, there are two ports available. In general,
when a peripheral is enabled, that pin may not be used
as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRISx registers (data direction register)
• PORTx registers (reads the levels on the pins of
• LATx registers (output latch)
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELx (analog select)
• WPUx (weak pull-up)
TABLE 12-1:
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports with analog functions also have an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure
 2011 Microchip Technology Inc.
Device
PIC16(L)F1826
PIC16(L)F1827
the device)
12-1.
I/O PORTS
PORT AVAILABILITY PER
DEVICE
●
●
●
●
●
FIGURE 12-1:
EXAMPLE 12-1:
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL PORTA
CLRF
BANKSEL LATA
CLRF
BANKSEL ANSELA
CLRF
BANKSEL TRISA
MOVLW
MOVWF
To peripherals
Write PORTx
Write LATx
Data Bus
Read PORTx
PIC16(L)F1826/27
PORTA
LATA
ANSELA
B'00111000' ;Set RA<5:3> as inputs
TRISA
Data Register
D
CK
Read LATx
ANSELx
GENERIC I/O PORT
OPERATION
INITIALIZING PORTA
Q
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;and set RA<2:0> as
;outputs
TRISx
DS41391D-page 117
V
V
DD
SS
I/O pin