PIC16F1826-I/ML Microchip Technology Inc., PIC16F1826-I/ML Datasheet - Page 25

• Manufacturer Part Number: PIC16F1826-I/ML
• Description: 28 QFN 6x6mm TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/ML

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

TABLE 3-3:
Legend:
80Bh
80Ch
800h
86Fh
870h
87Fh
C0Ch
C00h
C0Bh
C6Fh
C70h
C7Fh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh)
BANK16
(Accesses
BANK 24
Read as ‘0’
(Table
70h – 7Fh
Accesses
3-2)
3-2)
= Unimplemented data memory locations, read as ‘0’
PIC16(L)F1826/27 MEMORY MAP (CONTINUED)
88Bh
88Ch
8EFh
8FFh
880h
8F0h
C8Ch
CEFh
C80h
C8Bh
CF0h
CFFh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh)
BANK17
(Accesses
BANK 25
Read as ‘0’
(Table
70h – 7Fh
Accesses
3-2)
3-2)
90Bh
90Ch
900h
96Fh
970h
97Fh
D0Ch
D00h
D0Bh
D6Fh
D70h
D7Fh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
(Table
70h – 7Fh)
BANK18
(Accesses
BANK 26
Read as ‘0’
(Table
70h – 7Fh
Accesses
3-2)
3-2)
98Bh
98Ch
9EFh
9F0h
9FFh
980h
D8Bh
D8Ch
DEFh
DFFh
D80h
DF0h
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
70h – 7Fh)
(Table
BANK19
(Accesses
BANK 27
Read as ‘0’
(Table
70h – 7Fh
Accesses
3-2)
3-2)
A0Ch
A00h
A0Bh
A6Fh
A70h
A7Fh
E0Ch
E00h
E0Bh
E6Fh
E70h
E7Fh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
70h – 7Fh)
(Table
(Accesses
BANK20
Read as ‘0’
BANK 28
(Table
70h – 7Fh
Accesses
3-2)
3-2)
A8Ch
AEFh
AFFh
A80h
A8Bh
AF0h
E8Ch
EEFh
E80h
E8Bh
EF0h
EFFh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Read as ‘0’
70h – 7Fh)
BANK21
(Table
(Accesses
Read as ‘0’
BANK 29
(Table
70h – 7Fh
Accesses
3-2)
3-2)
B0Bh
B0Ch
B00h
B6Fh
B70h
B7Fh
F0Ch
F00h
F0Bh
F6Fh
F70h
F7Fh
Unimplemented
Core Registers
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
(Table
70h – 7Fh)
BANK22
(Accesses
Read as ‘0’
BANK 30
70h – 7Fh)
(Table
(Accesses
3-2)
3-2)
B8Bh
B8Ch
BEFh
BFFh
B80h
BF0h
F8Ch
FEFh
F80h
F8Bh
F9Fh
FA0h
FF0h
FFFh
Unimplemented
See
more information
Core Registers
Common RAM
Unimplemented
Core Registers
Common RAM
Read as ‘0’
(Table
70h – 7Fh)
BANK23
(Accesses
Read as ‘0’
BANK 31
(Table
70h – 7Fh)
(Accesses
Table 3-4
3-2)
3-2)
for