PIC16F1826-I/ML Microchip Technology Inc., PIC16F1826-I/ML Datasheet - Page 208

• Manufacturer Part Number: PIC16F1826-I/ML
• Description: 28 QFN 6x6mm TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/ML

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC16(L)F1826/27
24.3
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 24-3
signal.
24.3.1
The standard PWM function described in this section is
available and identical for CCP modules ECCP1,
ECCP2, CCP3 and CCP4.
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
• PRx registers
• TxCON registers
• CCPRxL registers
• CCPxCON registers
Figure 24-4
operation.
DS41391D-page 208
Note 1: The corresponding TRIS bit must be
2: Clearing the CCPxCON register will
PWM Overview
STANDARD PWM OPERATION
shows a simplified block diagram of PWM
cleared to enable the PWM output on the
CCPx pin.
relinquish control of the CCPx pin.
shows a typical waveform of the PWM
FIGURE 24-3:
FIGURE 24-4:
Note 1:
CCPRxH
Duty Cycle Registers
Comparator
2:
Pulse Width
CCPRxL
TMRx = 0
PRx
TMRx
Comparator
The 8-bit timer TMRx register is concatenated
with the 2-bit internal system clock (F
2 bits of the prescaler, to create the 10-bit time
base.
In PWM mode, CCPRxH is a read-only register.
(2)
Period
(Slave)
CCP PWM OUTPUT SIGNAL
(1)
SIMPLIFIED PWM BLOCK
DIAGRAM
Clear Timer,
toggle CCPx pin and
latch duty cycle
TMRx = CCPRxH:CCPxCON<5:4>
 2011 Microchip Technology Inc.
CCPxCON<5:4>
TMRx = PRx
S
R
Q
TRIS
OSC
CCPx
), or