PIC16F1826-I/ML Microchip Technology Inc., PIC16F1826-I/ML Datasheet - Page 173

• Manufacturer Part Number: PIC16F1826-I/ML
• Description: 28 QFN 6x6mm TUBE, 3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhance
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1826-I/ML

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin QFN
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 32 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

20.0
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
• TMR0 can be used to gate Timer1
Figure 20-1
20.1
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
20.1.1
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
FIGURE 20-1:
 2011 Microchip Technology Inc.
From CPSCLK
Note:
T0CKI
F
OSC
TIMER0 MODULE
Timer0 Operation
/4
8-BIT TIMER MODE
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
is a block diagram of the Timer0 module.
T0XCS
0
1
TMR0SE
BLOCK DIAGRAM OF THE TIMER0
TMR0CS
0
1
Prescaler
8-bit
8
PS<2:0>
20.1.2
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’ and resetting the T0XCS bit in the CPSCON0 register
to ‘0’.
8-Bit Counter mode using the Capacitive Sensing
Oscillator (CPSCLK) signal is selected by setting the
TMR0CS bit in the OPTION_REG register to ‘1’ and
setting the T0XCS bit in the CPSCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
PIC16(L)F1826/27
8-BIT COUNTER MODE
PSA
1
0
2 T
Sync
CY
Set Flag bit TMR0IF
DS41391D-page 173
Overflow to Timer1
on Overflow
Data Bus
8
TMR0