MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 215

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A match can initiate a transition to another state sequencer state (see
comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW,
SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW
bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte)
to be considered in the compare. Only comparators A and B feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator
qualifies a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction
reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored;
the comparator address register must be loaded with the exact opcode address.
If the TAG bit is clear (forced type match) a comparator match is generated when the selected address appears on the system
address bus. If the selected address is an opcode address, the match is generated when the opcode is fetched from the memory,
which precedes the instruction execution by an indefinite number of cycles due to instruction pipelining. For a comparator match
of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register.
Thus for an opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not verified again on
subsequent matches. Thus if a particular data value is verified at a given address, this address may not still contain that data
value when a subsequent match occurs.
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see
Register2
Priorities).
4.32.4.2.1
With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the
comparator address registers. Further qualification of the type of access (R/W, word/byte) and data bus contents is possible,
depending on comparator channel.
4.32.4.2.1.1
Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus with the comparator
address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match.
4.32.4.2.1.2
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is set the access size (word
or byte) is compared with the SZ bit value such that only the specified size of access causes a match. Thus if configured for a
byte access of a particular address, a word access covering the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are shown in
Freescale Semiconductor
Note:
178.
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain
the exact address from the code.
(DBGC2)). Comparator channel priority rules are described in the priority section
Read and write accesses of ADDR[n]
Condition For Valid Match
Write accesses of ADDR[n]
Read accesses of ADDR[n]
Single Address Comparator Match
Comparator C
Comparator B
Table 319. Comparator C Access Considerations
MM912_634 Advance Information, Rev. 4.0
Comp C Address
ADDR[n]
ADDR[n]
ADDR[n]
(178)
Section 4.32.4.4, “State Sequence
RWE
0
1
1
RW
X
0
1
(Section 4.32.4.3.4, “Channel
Section 4.32.3.2.4, “Debug Control
STAA #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
LDAA #$BYTE ADDR[n]
LDAA ADDR[n]
Examples
Control”). The
Table
320.
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