MM912H634CV1AER2 Freescale Semiconductor, MM912H634CV1AER2 Datasheet - Page 85

• Manufacturer Part Number: MM912H634CV1AER2
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AER2

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14
4.14.1
To control the High Side (HS1, HS2) and the Low Side (LS1, LS2) duty cycle as well as the PTB2 output, the PWM
module is implemented. Refer to the individual driver section for details on the use of the internal PWM1 and
PWM0 signal
I/O -
The PWM definition is based on the HC12 PWM definitions with some of the simplifications incorporated. The PWM module has
two channels with independent controls of left and center aligned outputs on each channel.
Each of the two channels has a programmable period and duty cycle as well as a dedicated counter. A flexible clock select
scheme allows a total of four different clock sources to be used with the counters. Each of the modulators can create independent
continuous waveforms with software-selectable duty rates from 0% to 100%.
4.14.1.1
The PWM block includes these distinctive features:
4.14.1.2
The PWM8B2C module does operate in Normal mode only.
4.14.1.3
Figure 22
Freescale Semiconductor
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PTB[0…2])
Two independent PWM channels with programmable periods and duty cycles
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM
counter reaches zero), or when the channel is disabled
Programmable center or left aligned outputs on individual channels
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
Programmable clock select logic
shows the block diagram for the 8-bit 2-channel PWM block.
D2D Clock
PWM Control Module (PWM8B2C)
(Section 4.12, “High Side Drivers -
Introduction
Features
Modes of Operation
Block Diagram
PWM8B2C
Clock Select
Control
Alignment
Polarity
Enable
MM912_634 Advance Information, Rev. 4.0
PWM Clock
Figure 22. PWM Block Diagram
HS,
Section 4.13, “Low Side Drivers - LSx
PWM Channels
Period and Duty
Period and Duty
Channel 1
Channel 0
Counter
Counter
and
PWM Control Module (PWM8B2C)
Section 4.18, “General Purpose
PWM0
PWM1
MCU
ANALOG
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