PIC32MX795F512LT-80V/BG Microchip Technology, PIC32MX795F512LT-80V/BG Datasheet - Page 239

• Manufacturer Part Number: PIC32MX795F512LT-80V/BG
• Description: 512 KB Flash, 128 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 1
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512LT-80V/BG

• Processor Series: PIC32MX7xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-100
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

APPENDIX A:
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
A.1
PIC32MX5XX/6XX/7XX
stopping DMA transfers in Idle mode.
A.2
PIC32MX5XX/6XX/7XX
interrupts for some of the peripheral modules. This
means that the interrupt condition for these peripherals
must be cleared before the interrupt flag can be
cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive
register to clear the interrupt condition and then clear
the associated UxIF flag to clear the pending UART
interrupt. In other words, the UxIF flag cannot be
cleared by software until the UART Receive register is
read.
TABLE A-1:
© 2009-2011 Microchip Technology Inc.
Input Capture
SPI
UART
ADC
PMP
Module
DMA
Interrupts
PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
MIGRATING FROM
PIC32MX3XX/4XX TO
PIC32MX5XX/6XX/7XX
DEVICES
devices
devices
do
have
not
persistent
support
Interrupt Implementation
Table A-1
interrupts
PIC32MX5XX/6XX/7XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
PIC32MX5XX/6XX/7XX
outlines the peripherals and associated
that
are
implemented
versus
DS61156G-page 239
PIC32MX3XX/4XX
differently
on