PIC32MX795F512LT-80V/BG Microchip Technology, PIC32MX795F512LT-80V/BG Datasheet - Page 74

• Manufacturer Part Number: PIC32MX795F512LT-80V/BG
• Description: 512 KB Flash, 128 KB RAM, USB-OTG, Dual CAN, Ethernet, 80 MHz, 10-Bit ADC, DMA 1
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512LT-80V/BG

• Processor Series: PIC32MX7xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-100
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-7:
Legend:
Note
10D0
10E0
10F0
1100
1120
1130
1140
1150
1110
1:
2:
3:
IPC10
IPC11
IPC12
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
Registers”
This bit is unimplemented on PIC32MX764F128L device.
This register does not have associated CLR, SET, and INV registers.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES
for more information.
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
(1)
DMA7IP<2:0>
DMA5IP<2:0>
CAN2IP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
DMA3IP<2:0>
DMA1IP<2:0>
INT4IP<2:0>
SPI1IP<2:0>
I2C1IP<2:0>
SPI2IP<2:0>
I2C4IP<2:0>
I2C2IP<2:0>
USBIP<2:0>
AD1IP<2:0>
IC4IP<2:0>
IC5IP<2:0>
(CONTINUED)
U3IP<2:0>
U5IP<2:0>
U4IP<2:0>
27/11
(2)
(2)
(2)
26/10
25/9
DMA7IS<1:0>
DMA5IS<1:0>
CAN2IS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
DMA3IS<1:0>
DMA1IS<1:0>
INT4IS<1:0>
SPI1IS<1:0>
I2C1IS<1:0>
SPI2IS<1:0>
I2C4IS<1:0>
I2C2IS<1:0>
USBIS<1:0>
AD1IS<1:0>
IC4IS<1:0>
IC5IS<1:0>
U3IS<1:0>
U5IS<1:0>
U4IS<1:0>
24/8
(2)
(2)
(2)
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/4
DMA6IP<2:0>
DMA4IP<2:0>
CMP2IP<2:0>
FSCMIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
CAN1IP<2:0>
OC4IP<2:0>
OC5IP<2:0>
SPI3IP<2:0>
I2C3IP<2:0>
PMPIP<2:0>
SPI4IP<2:0>
I2C5IP<2:0>
FCEIP<2:0>
ETHIP<2:0>
CNIP<2:0>
U1IP<2:0>
U2IP<2:0>
U6IP<2:0>
T4IP<2:0>
T5IP<2:0>
19/3
(2)
(2)
Section 12.1.1 “CLR, SET and INV
18/2
17/1
DMA6IS<1:0>
DMA4IS<1:0>
CMP2IS<1:0>
FSCMIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
CAN1IS<1:0>
OC4IS<1:0>
OC5IS<1:0>
SPI3IS<1:0>
I2C3IS<1:0>
PMPIS<1:0>
SPI4IS<1:0>
I2C5IS<1:0>
FCEIS<1:0>
ETHIS<1:0>
CNIS<1:0>
U1IS<1:0>
U2IS<1:0>
U6IS<1:0>
T4IS<1:0>
T5IS<1:0>
16/0
(2)
(2)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000