STM32W108CBU61TR STMicroelectronics, STM32W108CBU61TR Datasheet - Page 139

• Manufacturer Part Number: STM32W108CBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108CBU61TR

• Applications: RF4CE, Remote Control
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 24
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM32W108CB, STM32W108HB
10.3
10.3.1
31
15
30
14
Bits [6:5] TIM_CMS: Center-aligned Mode Selection
General-purpose timer (1 and 2) registers
Timer x control register 1 (TIMx_CR1)
Address offset: 0xE000 (TIM1) and 0xF000 (TIM2)
Reset value:
Bit 7 TIM_ARBE: Auto-Reload Buffer Enable
Bit 4 TIM_DIR: Direction
Bit 3 TIM_OPM: One Pulse Mode
Bit 2 TIM_URS: Update Request Source
29
13
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(TIM_DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively.
Output compare interrupt flags of configured output channels (TIM_CCyS=00 in TIMx_CCMRy
register) are set both when the counter is counting up or down.
Note: Software may not switch from edge-aligned mode to center-aligned mode when the
0: Counter used as up-counter.
1: Counter used as down-counter.
0: Counter does not stop counting at the next update event.
1: Counter stops counting at the next update event (and clears the bit TIM_CEN).
0: When enabled, update interrupt requests are sent as soon as registers are updated (counter
overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode
controller).
1: When enabled, update interrupt requests are sent only when the counter reaches overflow or
underflow.
28
12
Reserved
counter is enabled (TIM_CEN=1).
27
11
0x0000 0000
26
10
25
9
Doc ID 16252 Rev 8
24
8
Reserved
TIM_A
RBE
23
rw
7
22
6
TIM_CMS
rw
21
5
TIM_D
20
rw
IR
4
General-purpose timers
TIM_O
PM
19
rw
3
TIM_U
RS
18
rw
2
TIM_U
DIS
17
rw
1
139/209
TIM_C
EN
16
rw
0