MT29F1G08ABBDAH4-IT:D Micron Technology Inc, MT29F1G08ABBDAH4-IT:D Datasheet
MT29F1G08ABBDAH4-IT:D
Specifications of MT29F1G08ABBDAH4-IT:D
Available stocks
Related parts for MT29F1G08ABBDAH4-IT:D
MT29F1G08ABBDAH4-IT:D Summary of contents
Page 1
... NAND Flash Memory MT29F1G08ABADAWP, MT29F1G08ABBDAH4, MT29F1G08ABBDAHC, MT29F1G16ABBDAH4, MT29F1G16ABBDAHC, MT29F1G08ABADAH4 Features • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – ...
Page 2
... Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Marketing Part Number Chart ...
Page 3
... One-Time Programmable (OTP) Operations .................................................................................................... 64 OTP DATA PROGRAM (80h-10h) ................................................................................................................. 65 RANDOM DATA INPUT (85h) .................................................................................................................... 66 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Features ...
Page 4
... Rev C, Preliminary – 4/10 ............................................................................................................................ 93 Rev B, Preliminary – 3/10 ............................................................................................................................ 93 Rev A, Preliminary – 2/10 ............................................................................................................................ 93 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Features ...
Page 5
... Table 26: DC Characteristics and Operating Conditions (1.8V) ........................................................................ 81 Table 27: ProgramErase Characteristics ......................................................................................................... 82 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Features ...
Page 6
... Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11 Figure 5: 48-Pin TSOP – Type 1, CPL .............................................................................................................. 12 Figure 6: 63-Ball VFBGA (HC) ........................................................................................................................ 13 Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm ................................................................................................... 14 Figure 8: NAND Flash Die (LUN) Functional Block Diagram ........................................................................... 15 Figure 9: Array Organization – x8 ................................................................................................................... 16 Figure 10: Array Organization – x16 ................................................................................................................ 17 Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19 Figure 12: Asynchronous Address Latch Cycle ...
Page 7
... Figure 69: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 91 Figure 70: INTERNAL DATA MOVE ................................................................................................................ 92 Figure 71: ERASE BLOCK Operation ............................................................................................................... 92 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Features ...
Page 8
... NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization. ...
Page 9
... PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/ Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Signal Assignments x8 x16 48 Vss 1 Vss 47 DNU I/O15 46 NC I/O14 45 NC I/O13 44 I/O7 I/O7 43 I/O6 I/O6 42 I/O5 I/O5 41 I/O4 I/O4 ...
Page 10
... These pins might not be bonded inthe package; however, Micron recommends that the Note: customer connect these pins to the designated external sources for ONFI compatibility. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory WP# ALE Vss CE# WE# R/B# Vcc 2 RE# ...
Page 11
... Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory WP# ALE Vss CE# WE# R/B# Vcc RE# CLE Vss DNU Vcc NC I/O13 I/O15 DNU I/O8 I/O0 I/O10 I/O12 I/O14 Vcc I/O9 I/O1 I/O11 Vcc ...
Page 12
... All dimensions are in millimeters. Note: PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 20.00 ±0.25 18.40 ±0. See detail A 1.20 MAX 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. Package Dimensions ...
Page 13
... TYP 7.2 CTR 10.5 ±0.1 Bottom side saw fiducials may or may not be covered with soldermask. 13 1Gb x8, x16: NAND Flash Memory Package Dimensions Ball A1 ID 1.0 MAX 0.25 MIN Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. ...
Page 14
... Bottom side saw fiducials may or 9 ±0.1 may not be covered with soldermask. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Package Dimensions Ball A1 ID 1.0 MAX 0.25 MIN © 2010 Micron Technology, Inc. All rights reserved. ...
Page 15
... The addresses are latched by an address register and sent to a row decoder to select a row address column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. ...
Page 16
... If CA11 is 1, then CA[10:6] must be 0. Notes: 2. Block address concatenated with page address = actual page address; CAx = column ad- dress; PAx = page address; BAx = block address. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Device and Array Organization 2112 bytes 2048 64 I/O7 ...
Page 17
... Block address concatenated with page address = actual page address. CAx = column ad- dress; PAx = page address; BAx = block address. 3. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 1056 words 1024 32 1024 ...
Page 18
... This helps reduce power con- sumption. The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn- chronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus ...
Page 19
... Figure 11: Asynchronous Command Latch Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Bus Operation t t CLS CLH ALS ALH COMMAND 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 20
... ALS t ALH Col Col Row add 1 add 2 add 1 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Row Row add 2 add 3 Don’t Care Undefined © 2010 Micron Technology, Inc. All rights reserved. ...
Page 21
... ALE I/Ox PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN Asynchronous Interface Bus Operation M Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t CLH © 2010 Micron Technology, Inc. All rights reserved. Don’t Care ...
Page 22
... Asynchronous Data Output Data can be output from a die (LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH. ...
Page 23
... RP t REH t REA t REA t RLOH D D OUT OUT 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t CHZ t COH t RHZ t RHOH D OUT Don’t Care before issu- © 2010 Micron Technology, Inc. All rights reserved. ...
Page 24
... The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and V Where Σ Figure 16: READ/BUSY# Open Drain PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Bus Operation × (MAX (MAX ...
Page 25
... Fall t Rise – Rise calculated at 10% and 90% points Fall - Rise are calculated at 10% and 90% points. 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory 3. Rise 1.8V CC © 2010 Micron Technology, Inc. All rights reserved. ...
Page 26
... Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory 8000 10,000 12,000 Rp (Ω (MAX 6000 8000 10,000 Rp (Ω © 2010 Micron Technology, Inc. All rights reserved. ...
Page 27
... Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory 6000 8000 10,000 12,000 (MAX) Rp (Ω 100pF © 2010 Micron Technology, Inc. All rights reserved. ...
Page 28
... The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for 1ms after a RESET command is issued. The RESET busy time can be monitored by polling issuing the READ STATUS (70h) command to poll the status register. ...
Page 29
... Yes 80h 4 Yes 60h 3 00h 4 85h Optional 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Command Definitions Valid While Command Selected LUN is 1 Cycle #2 Busy – – Yes – – No – – ...
Page 30
... Input Cycles Cycles 80h 4 No 80h 4 Yes 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Command Definitions Valid While Command Selected LUN is 1 Cycle #2 Busy 10h No 10h No 30h No © 2010 Micron Technology, Inc. All rights reserved. ...
Page 31
... The RESET command must be issued to all CE#s as the first command after power-on. The device will be busy for a maximum of 1ms. Figure 23: RESET (FFh) Operation Cycle type I/O[7:0] R/B# PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory t RST after the RESET command is written to the Command ...
Page 32
... See the READ ID Parameter tables for byte definitions. Note: Figure 25: READ ID (90h) with 20h Address Operation Cycle type I/O[7:0] 1. See READ ID Parameter tables for byte definitions. Note: PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Command Address D OUT t WHR 90h 00h ...
Page 33
... MT29F1G16ABBDA Byte 4 Internal ECC level 4-bit ECC/512 (main (spare (parity) bytes Planes per CE# 1 Plane size 1Gb Internal ECC ECC disabled ECC enabled PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory READ ID Parameter Tables I/07 I/06 I/05 I/04 I/ ...
Page 34
... Options Byte value MT29F1G08ABADA MT29F1G08ABBDA MT29F1G16ABBDA Table 7: READ ID Parameters for Address 20h h = hexadecimal Byte Options I/07 “O” “N” “F” “I” Undefined X PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory I/07 I/06 I/ I/06 I/05 I/04 I/ ...
Page 35
... Cycle type Command Address I/O[7:0] ECh R/B# PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/ OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory READ PARAMETER PAGE (ECh OUT OUT OUT OUT P1 … © 2010 Micron Technology, Inc. All rights reserved. ...
Page 36
... MT29F1G08ABBDAH4 4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h, 42h, 42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h ...
Page 37
... MT29F1G16ABBDA3W 1Fh, 00h MT29F1G08ABADAWP 3Fh, 00h MT29F1G08ABBDAHC 1Fh, 00h MT29F1G16ABBDAHC 1Fh, 00h MT29F1G08ABBDAH4 1Fh, 00h MT29F1G16ABBDAH4 1Fh, 00h MT29F1G08ABADAH4 3Fh, 00h 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. ...
Page 38
... MT29F1G08ABBDA3W 1Fh, 00h MT29F1G16ABBDA3W 1Fh, 00h MT29F1G08ABADAWP 3Fh, 00h MT29F1G08ABBDAHC 1Fh, 00h MT29F1G16ABBDAHC 1Fh, 00h MT29F1G08ABBDAH4 1Fh, 00h MT29F1G16ABBDAH4 1Fh, 00h MT29F1G08ABADAH4 3Fh, 00h 58h, 02h B8h, 0Bh 19h, 00h 64h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, ...
Page 39
... Cycle type Command Address I/O[7:0] EDh R/B# PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/ OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory READ UNIQUE ID (EDh OUT OUT OUT OUT U1 … © 2010 Micron Technology, Inc. All rights reserved. ...
Page 40
... The sequence to disable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)- 00h(data)-00h(data)-00h(data)-00h(data)-wait( is EEh. Table 9: Feature Address Definitions Feature Address PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Definition 00h Reserved 01h Timing mode 02h–7Fh ...
Page 41
... Reserved (0) 0 Reserved (0) 1 Reserved (0) Reserved (0) Reserved (0) Command Address ADL I/O[7:0] EFh FA P1 R/B# 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Feature Operations I/O2 I/O1 I/O0 Value 0 00h 1 01h 1 1 03h 00h 0 0 ...
Page 42
... After FEAT completes, the host enables data output mode to read the subfeature param- eters. Figure 29: GET FEATURES (EEh) Operation Cycle type I/Ox R/B# PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Command Address EEh FEAT Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 43
... Supported timing modes are reported in the parame- ter page. 2. Supported for both 1.8V and 3.3V. 3. Supported for 3.3V only. 4. Not supported. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 Reserved (0) ...
Page 44
... This feature address is used to change the default R/B# pull-down strength. Its strength Note: should be selected based on the expected loading of R/B#. Full strength is the default, power-on value. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 ...
Page 45
... I/O[7:0] as long as CE# and RE# are LOW not necessary to toggle RE# to see the status register update. While monitoring the status register to determine when a data transfer from the Flash array to the data register ( command to disable the status register and enable data output (see Read Operations). ...
Page 46
... If there is only one die (LUN) per target, the READ STATUS (70h) command can be used to return status following any NAND command. Figure 30: READ STATUS (70h) Operation Cycle type I/O[7:0] PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Command D OUT t WHR 70h ...
Page 47
... Rev. D 06/10 EN Command Address Address Command t RHW 05h Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Column Address Operations D D OUT OUT t WHR E0h © 2010 Micron Technology, Inc. All rights reserved. ...
Page 48
... The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and ena- bles data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1 ...
Page 49
... The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the RAN- DOM DATA READ (05h-E0h) command to read and modify cache register contents in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller. ...
Page 50
... NAND Flash array to the data register. To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. ...
Page 51
... This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To read a page from the NAND Flash array, write the 00h command to the command register, then write n address cycles to the address registers, and conclude with the 30h command ...
Page 52
... RCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
Page 53
... ARDY = 0) for busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
Page 54
... Page Address Command D OUT 31h RCBSY RR Page N 54 1Gb x8, x16: NAND Flash Memory Read Operations D D OUT OUT 31h D0 … RCBSY RR Page M Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. D Command ...
Page 55
... RCBSY, R/B# goes HIGH and the die (LUN Command OUT OUT OUT D0 … D 3Fh Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Read Operations D D OUT OUT D0 … RCBSY RR Page N © 2010 Micron Technology, Inc. All rights reserved. D ...
Page 56
... Program Operations The PROGRAM PAGE (80h-10h) command programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. Program Cache Operations The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op- eration system performance ...
Page 57
... CBSY, the host can monitor the target's R/B# signal or, t CBSY, the host wants to wait for the program cache operation to complete, with- 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Program Operations Command ...
Page 58
... Rev. D 06/10 EN Address Address ADL Address Address ADL Address Address ADL Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Program Operations Command … Dn 15h Command … Dn 15h Command … ...
Page 59
... Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully ...
Page 60
... PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Internal Data Move Operations 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 61
... Address Address Command Address Address Address Command 35h Address Command D t WHR C2 E0h Dk 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Internal Data Move Operations D D OUT OUT 35h OUT OUT D0 … ...
Page 62
... OUT D is optional Destination address SR bit READ successful OUT SR bit READ error 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Internal Data Move Operations t PROG_ECC Address 85h 10h 70h Status (4 cycles) Destination address ...
Page 63
... Address Address Address Address Address 85h Address Address WHR Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Internal Data Move Operations Command 10h PROG WHR Command 10h PROG © 2010 Micron Technology, Inc. All rights reserved. ...
Page 64
... One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area any way they choose ...
Page 65
... Status Operations). Each OTP page can be programmed to 8 partial-page programming. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory One-Time Programmable (OTP) Operations 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 66
... I/Ox 80h add 1 add 2 OTP DATA INPUT command OTP address R/B# 1. The OTP page must be within the 02h–1Fh range. Note: PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory One-Time Programmable (OTP) Operations D D OTP 00h IN IN page ...
Page 67
... Col 00h 85h add1 add2 Serial input RANDOM DATA Column address INPUT command t OBSY. 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory PROG D D 10h IN IN 70h Serial input PROGRAM READ STATUS command command Don‘ ...
Page 68
... PROGRAM command OTP address 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t PROG Status 70h READ STATUS command OTP data protected Don’t Care © 2010 Micron Technology, Inc. All rights reserved. ...
Page 69
... One-Time Programmable (OTP) Operations t R) while the data is moved from the OTP page to the data register. The Col OTP 00h page 1 OTP address 69 1Gb x8, x16: NAND Flash Memory 30h OUT OUT Busy Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 70
... 00h 30h OUT OUT Busy 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t CLR t WHR t REA Col Col D 05h E0h OUT add 1 add 2 m Column address m Don’t Care © 2010 Micron Technology, Inc. All rights reserved. ...
Page 71
... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: • Always check status after a PROGRAM or ERASE operation • ...
Page 72
... Description Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Error Management Requirement 1-bit ECC per 528 bytes 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 73
... No 837h 834h Yes 83Fh 838h Yes PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Internal ECC and Spare Area Mapping for ECC Area Description Main 0 User data Main 1 User data Main 2 User data Main 3 User data Reserved User metadata II ...
Page 74
... No 41Bh 41Ah Yes 41Fh 41Ch Yes PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Internal ECC and Spare Area Mapping for ECC Area Description Main 0 User data Main 1 User data Main 2 User data Main 3 User data Reserved User metadata II ...
Page 75
... Do not erase or program blocks marked invalid by the factory. 2. Blocks 0–7 (3.3V) and blocks 0–3 (1.8V) are guaranteed to be valid with ECC when ship- ped from the factory. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory SS Symbol Min 3.3V V – ...
Page 76
... Parameter Input pulse levels Input rise and fall times Input and output timing levels Output load 1. These parameters are verified in device characterization and are not 100% tested. Note: PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Symbol Max 25° ...
Page 77
... 100 t ADL begins in the address cycle on the final rising edge of WE#, and ends 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Conditions Max Unit – ns – ns – ns – ns – ns – ns – ns – ns – ...
Page 78
... RR t RST WHR Symbol CEA t CHZ t CLR t COH REA t REH t RHOH t RHW 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Conditions Min Max Unit – – – – – – – – – – ...
Page 79
... Rev. D 06/10 EN Electrical Specifications – AC Characteristics and Operating Symbol t RHZ t RLOH RST WHR 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Conditions Min Max Unit – – – – – 5/10/500 µ ...
Page 80
... R/B pull-down strength is not set to full. and V may need to be relaxed if I/O drive strength is not set to full Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Typ Max Unit – – ...
Page 81
... V 0 WP# – V –0 –100µ +100µ 0.2V I (R/B and Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Typ Max Unit – – – – – – µA – – 10 per die mA – ...
Page 82
... Typical is nominal voltage and room temperature. 5. Typical 6. Data transfer from Flash array to data register with internal ECC disabled characteristics may need to be relaxed if I/O drive strength is not set to full. 8. Typical program time is defined as the time within which more than 50% of the pages are programmed at nominal voltage and room temperature ...
Page 83
... CE WE# R/B# FFh I/O[7:0] RESET command Figure 57: READ STATUS Cycle CLE CE# WE# RE# I/O[7:0] PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams t RST t CLR t CLS t CLH CEA t WHR 70h 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 84
... Asynchronous Interface Timing Diagrams R_ECC R_ECC Row Row Col 30h add 1 add 2 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory P255 CLR OUT OUT Busy © 2010 Micron Technology, Inc. All rights reserved. t RHZ D ...
Page 85
... Figure 60: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE RDY WE# I/Ox 00h Address (4 cycles) PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams R_ECC 30h t CEA CE REA CHZ t RE# COH Out I/Ox 85 Micron Technology, Inc ...
Page 86
... CLE CE# WE# ALE t RC RE# D I/Ox OUT RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams t RHW Col Col D 05h OUT add 1 add 2 N Column address M 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 87
... CEA REA 31h OUT OUT D OUT 0 1 Page address t RCBSY Column address 0 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t t CLS CLH CEA RHW REA OUT OUT 31h OUT 0 1 Page address ...
Page 88
... REA D D 31h OUT OUT RCBSY Page address M Column address 0 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory Col Col Row Row 00h add 1 add 2 add 1 add 2 Column address Page address 00h N ...
Page 89
... Address, 1 cycle Figure 65: PROGRAM PAGE Operation CLE CE WE# ALE RE# Col Col I/Ox 80h add 1 add 2 RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams WHR REA Byte 0 Byte 1 t ADL D D Row Row IN IN ...
Page 90
... Figure 67: PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE WE# ALE RE# Col Col Row Row i/Ox 80h add 1 add 2 add 1 add 2 RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams Data input CE WE# t ADL t ADL D D Col Col IN IN ...
Page 91
... M D Col Col Row Row IN 15h 70h Status 80h add 1 add 2 add 1 add Micron Technology, Inc. reserves the right to change products or specifications without notice. 1Gb x8, x16: NAND Flash Memory t ADL LPROG Row Row D D Col IN IN 10h add 1 add Last page ...
Page 92
... Figure 71: ERASE BLOCK Operation CLE CE WE# ALE RE# Row Row I/O[7:0] 60h add 1 add 2 Row address RDY PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory Asynchronous Interface Timing Diagrams 35h Col Col Row Row 85h (or 30h) add 1 add 2 add 1 add 2 Busy ...
Page 93
... This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. PDF: 09005aef83e5ffed m68a.pdf – Rev. D 06/10 EN 1Gb x8, x16: NAND Flash Memory 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. ...