LH7A404N0F092B3 NXP Semiconductors, LH7A404N0F092B3 Datasheet - Page 65

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LH7A404N0F092B3

Manufacturer Part Number
LH7A404N0F092B3
Description
Microcontrollers (MCU) LCD USB FS/HOST MMU LFBGA324
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LH7A404N0F092B3

Data Bus Width
32 bit
Program Memory Type
ROMLess
Data Ram Size
80 KB
Interface Type
AC97, EBI, IrDA, Microwire, SPI, SSI, SSP, UART, USB
Maximum Clock Frequency
266 MHz
Number Of Programmable I/os
64
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LFBGA
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / Rohs Status
 Details
Other names
LH7A404N0F092B3;55

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32-Bit System-on-Chip
NOTE: *The timing relationship is specified as a cycle-based timing. Due to variations in crystal input clock jitter,
Preliminary data sheet
tDA_nURESET_nRSTO
tDD_nURESET_nRSTO
tA_nURESET
tDD_nURESET_WKUP
tA_WKUP
tDA_nURESET_CLKEN
tDA_WKUP_CLKEN
nRESETOUT
nURESET
WAKEUP
CLKEN
add some timing margin to avoid any possible corner case condition.
power rail noise and I/O conditioning these timings will vary marginally. It is recommended that designers
TRIGGER
SIGNAL
POINT
tDA_nURESET_CLKEN
tDA_nURESET_nRSTO
Table 15. nRESETOUT Timing Values for nURESET Trigger
MIN. TYP.
2
0
4
2
4
2
2
Figure 50. nRESETOUT Timing for nURESET Trigger
tA_nURESET
MAX.
4
2
4
4
XTAL32 Periods*
XTAL32 Periods*
XTAL32 Periods*
XTAL32 Periods*
XTAL32 Periods*
XTAL32 Periods*
XTAL32 Periods*
NXP Semiconductors
UNITS
tDD_nURESET_nRSTO
tDD_nURESET_WKUP
nURESET to nRESETOUT assertion delay
nURESET to nRESETOUT deassertion delay
nURESET assertion time
nURESET deassertion to WAKEUP assertion delay
WAKEUP assertion time
nURESET assertion to CLKEN deassertion delay
WAKEUP to CLKEN assertion delay
tDA_WKUP_CLKEN
DESCRIPTION
tA_WKUP
LH7A404
LH7A404-201
65

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