SAA7114HV2 NXP Semiconductors, SAA7114HV2 Datasheet - Page 107

• Manufacturer Part Number: SAA7114HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7114HV2

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
SAA7114_3
Product data sheet
Table 91:
[1]
Table 92:
[1]
[2]
Table 93:
I port FIFO flag control and arbitration
FAE FIFO flag almost empty level
FAF FIFO flag almost full level
Output clock and gated clock phase control
ICLK default output phase
ICLK phase shifted by
recommended for ICKS1 = 1 and ICKS0 = 0
(subaddress 80h)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by
approximately 3 ns
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
recommended for gated clock output
IDQ = gated clock phase shifted by approximately
3 ns
IDQ = gated clock phase shifted by
approximately 3 ns
I port I/O enable
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
< 16 Dwords
< 8 Dwords
< 4 Dwords
0 Dwords
32 Dwords
X = don’t care.
X = don’t care.
IPCK3 and IPCK2 only affects the gated clock (subaddress 80h, bit ICKS2 = 1).
16 Dwords
24 Dwords
28 Dwords
I port FIFO flag control and arbitration; global set 86h[3:0]
I port I/O enable, output clock and gated clock phase control; global set
87h[7:4]
I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]
[1]
alternatively to setting ‘01’
alternatively to setting ‘01’
1
1
Rev. 03 — 17 January 2006
2
2
clock cycle
clock cycle +
1
1
2
2
clock cycle
clock cycle +
Control bits D3 to D0
FFL1
X
X
X
X
0
0
1
1
Control bits D7 to D4
IPCK3
X
X
X
X
0
0
1
1
PAL/NTSC/SECAM video decoder
Control bits D1 and D0
IPE1
0
0
1
1
[2]
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
FFL0
X
X
X
X
0
1
0
1
IPCK2
X
X
X
X
0
1
0
1
[2]
[1]
SAA7114
FEL1
0
0
1
1
X
X
X
X
IPCK1
0
0
1
1
X
X
X
X
IPE0
0
1
0
1
FEL0
0
1
0
1
X
X
X
X
IPCK0
0
1
0
1
X
X
X
X
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