CS82C55AZ96 Intersil, CS82C55AZ96 Datasheet - Page 10

• Manufacturer Part Number: CS82C55AZ96
• Description: IC I/O EXPANDER 24B 44PLCC
• Manufacturer: Intersil

Specifications of CS82C55AZ96

• Interface: Programmable
• Number Of I /o: 24
• Interrupt Output: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency - Clock: -
• Other names: CS82C55AZ96TR

INTR (Interrupt Request)
A “high” on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the condition: STB is a “one”, IBF is a “one” and INTE is a
“one”. It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.
INTE A
Controlled by bit set/reset of PC4.
INTE B
Controlled by bit set/reset of PC2.
Output Control Signal Definition
(Figure 8 and 9)
OBF - (Output Buffer Full F/F). The OBF output will go “low”
to indicate that the CPU has written data out to the specified
port. This does not mean valid data is sent out of the port at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
ACK - (Acknowledge Input). A “low” on this input informs the
82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).
INTR - (Interrupt Request). A “high” on this output can be
used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a “one”, OBF is a “one” and INTE is a “one”. It is reset
by the falling edge of WR.
PERIPHERAL
INPUT FROM
INTR
STB
IBF
RD
10
tPS
tSIB
FIGURE 7. MODE 1 (STROBED INPUT)
tST
82C55A
tSIT
tPH
INTE A
Controlled by Bit Set/Reset of PC6.
INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
CONTROL WORD
D7
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1. To strobe data into the peripheral device, the user must operate
1
1
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the
peripheral device and then latch data into the peripheral device
on the rising edge of OBF.
D6
0
D5
1
tRIT
D4
1
1/0
D3 D2 D1 D0
FIGURE 8. MODE 1 OUTPUT
1
PC4, PC5
1 = INPUT
0 = OUTPUT
WR
WR
0
tRIB
MODE 1 (PORT A)
MODE 1 (PORT B)
INTE
INTE
A
B
PC4, PC5
PB7-PB0
PA7-PA0
PC7
PC6
PC3
PC1
PC2
PC0
November 16, 2006
2
FN2969.10
8
8
OBFA
ACKA
INTRA
OBFB
ACKB
INTRB