CS82C55A Intersil, CS82C55A Datasheet - Page 11

• Manufacturer Part Number: CS82C55A
• Description: IC I/O EXPANDER 24B 44PLCC
• Manufacturer: Intersil

Specifications of CS82C55A

• Interface: Programmable
• Number Of I /o: 24
• Interrupt Output: No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Chip Configuration: 8 Bit
• Bus Frequency: 8MHz
• No. Of I/o's: 24
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: LCC
• No. Of Pins: 44
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency - Clock: -

Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications.
Operating Modes
Mode 2 (Strobed Bidirectional Bus I/O)
This functional configuration provides a means for
communicating with a peripheral device or structure on a
single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt
generation and enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
• Used in Group A only
• One 8-bit, bidirectional bus Port (Port A) and a 5-bit
• Both inputs and outputs are latched
• The 5-bit control port (Port C) is used for control and
Bidirectional Bus I/O Control Signal Definition
(Figures 11, 12, 13, 14)
INTR - (Interrupt Request). A high on this output can be
used to interrupt the CPU for both input or output operations.
control Port (Port C)
status for the 8-bit, bidirectional bus port (Port A)
CONTROL WORD
D7
1
D6
0
OUTPUT
D5
1
INTR
ACK
OBF
WR
D4
1
D3 D2 D1 D0
1/0
1
RD
PC6, PC7
1 = INPUT
0 = OUTPUT
WR
0
11
PORT B - (STROBED OUTPUT)
PORT A - (STROBED INPUT)
tWIT
PC6, PC7
PB7, PB0
PA7-PA0
FIGURE 10. COMBINATIONS OF MODE 1
FIGURE 9. MODE 1 (STROBED OUTPUT)
PC4
PC5
PC3
PC1
PC2
PC0
2
8
8
STBA
IIBFA
INTRA
OBFB
ACKB
INTRB
tWOB
82C55A
I/O
tWB
CONTROL WORD
D7
1
Output Operations
OBF - (Output Buffer Full). The OBF output will go “low” to
indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A “low” on this input enables the three-
state output buffer of port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF).
Controlled by bit set/reset of PC4.
Input Operations
STB - (Strobe Input). A “low” on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A “high” on this output indicates
that data has been loaded into the input latch.
INTE 2 - (The INTE flip-flop associated with IBF). Controlled
by bit set/reset of PC4.
D6
0
D5
1
D4
tAK
0
tAOB
1/0
D3 D2 D1 D0
1
PC4, PC5
1 = INPUT
0 = OUTPUT
WR
RD
1
tAIT
PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)
PC4, PC5
PB7, PB0
PA7-PA0
PC7
PC6
PC3
PC2
PC1
PC0
November 16, 2006
2
8
8
OBFA
ACKA
INTRA
STBB
IBFB
INTRB
FN2969.10
I/O