PCA8574ATS,118 NXP Semiconductors, PCA8574ATS,118 Datasheet - Page 15

• Manufacturer Part Number: PCA8574ATS,118
• Description: IC I/O EXPANDER I2C 8B 20SSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA8574ATS,118

• Package / Case: 20-SSOP
• Interface: I²C
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: PCA8574
• Number Of Lines (input / Output): 8.0 / 8.0
• Operating Supply Voltage: 2.3 V to 5.5 V
• Power Dissipation: 400 mW
• Operating Temperature Range: - 40 C to + 85 C
• Input Voltage: 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Current: 50 mA
• Output Voltage: 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935283491118; PCA8574ATS-T; PCA8574ATS-T

NXP Semiconductors
13. Dynamic characteristics
Table 8.
V
[1]
[2]
[3]
[4]
[5]
[6]
PCA8574_PCA8574A_2
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing; C
t
t
t
Interrupt timing; C
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
HD;DAT
VD;ACK
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(D)
d(rst)
DD
= 2.3 V to 5.5 V; V
t
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Parameter
SCL clock frequency
bus free time between a STOP and START
condition
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be suppressed
by the input filter
data output valid time
data input set-up time
data input hold time
data input valid time
reset delay time
Dynamic characteristics
L
f
100 pF (see
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
L
SS
100 pF (see
= 0 V; T
[2]
[6]
Figure 8
amb
f
.
Figure 8
= 40 C to +85 C; unless otherwise specified. Limits are for Fast-mode I
[1]
and
Figure
and
Figure
Rev. 02 — 14 May 2007
9)
9)
Conditions
Remote 8-bit I/O expander for I
[3][4]
Min
0
1.3
0.6
0.6
0.6
0
0.1
50
100
1.3
0.6
20 + 0.1C
20 + 0.1C
-
-
0
4
-
-
PCA8574/74A
b
b
[5]
[5]
IL
of the SCL signal) in order to
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
C-bus with interrupt
© NXP B.V. 2007. All rights reserved.
Max
400
-
-
-
-
-
0.9
-
-
-
-
300
300
50
4
-
-
4
4
f
2
is specified at
C-bus.
Unit
kHz
ns
ns
ns
ns
ns
ns
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