MCIMX534AVV8C Freescale Semiconductor, MCIMX534AVV8C Datasheet
MCIMX534AVV8C
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MCIMX534AVV8C Summary of contents
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... The flexibility of the i.MX53xA architecture allows for its use in a wide variety of applications. As the heart of This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX53AEC Rev. 3, 7/2011 MCIMX53xA ...
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... For detailed information about the i.MX53xA security features contact a Freescale representative. The i.MX53xA application processor is a follow-on to the i.MX51xA, with improved performance, power efficiency, and multimedia capabilities. i.MX53xA Automotive and Infotainment Applications Processors, Rev ® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/ serial audio, among others). Freescale Semiconductor ...
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... Part Number Mask Set MCIMX536AVV8C N78C PCIMX536AVV8C N78C MCIMX534AVV8C N78C 1 Part numbers with a PC prefix indicate non production engineering parts. 2 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3. 1.2 Features The i.MX53xA multimedia applications processor (AP) is based on the ARM Platform, which has the following features: • ...
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... LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports MP/s (for example, WXGA at 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60). • Camera sensors: i.MX53xA Automotive and Infotainment Applications Processors, Rev NOTE Freescale Semiconductor ...
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... On-chip oscillator amplifier supporting 32.768 kHz external crystal • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Introduction 5 ...
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... SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization The actual feature set depends on the part number as described in Functions such as video hardware acceleration with 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. i.MX53xA Automotive and Infotainment Applications Processors, Rev NOTE Table 1. Freescale Semiconductor ...
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... Audio, Power Mngmnt. Ethernet 10/100 Mbps IrDA XVR The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor NOR/NAND Battery Ctrl Camera LVDS Camera Flash Device (2) (WSXGA+) (2) ...
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... The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. Table 2 describes these Freescale Semiconductor ...
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... Connectivity Audio Interface Peripherals i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). ...
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... EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. Freescale Semiconductor ...
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... IC Identification Security Module i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports bits of I/O. Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register ...
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... The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and data FIFO to generate sound. Brief Description ® data network, using Freescale Semiconductor ...
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... SCCv2 Security Security Controller, ver. 2 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Brief Description Internal RAM, shared with VPU. The on-chip memory controller (OCRAM) module interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. ...
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... JTAG security modes that can be selected through an e-fuse configuration. SPBA (shared peripheral bus arbiter two-to-one IP bus interface (IP bus) arbiter. A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Both transmitter and receiver functionalists are supported. Freescale Semiconductor ...
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... ARM/Control Interrupt Controller i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Brief Description The SRTC incorporates a special system state retention register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW ...
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... MJPEG encode, Baseline profile 8192 x 8192 resolution, 80 Mpixel/s bit rate for 4:2:2 format The watch dog timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line Freescale Semiconductor ...
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... This section provides the device-level electrical characteristics for the IC. See to the individual tables and sections. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Brief Description The TrustZone watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode ...
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... Table 4 on page 18 Table 5 on page 19 Table 6 on page 20 Table 7 on page 22 Table 8 on page 22 Table 9 on page 24 Min Max Unit –0.3 1.35 V –0.3 1.35 V –0.5 3.6 V –0.5 3.3 V — 5. –0.3 3. –0.5 OVDD +0 — 2000 — 500 o –40 150 C Freescale Semiconductor ...
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... Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Board 1, 2 Single layer board (1s ...
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... Freescale Semiconductor Unit ...
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... VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Parameter Minimum 2 ...
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... See Table 32, "CAMP Electrical Parameters (CKIH1, ckih1 f CKIH2)," on page 46 ckih2 f 22 xtal Table 8. Maximal Supply Currents Conditions 800 MHz ARM clock. Typ Max Unit 2 /32.0 — kHz MHz 24 27 MHz Max Current Unit 1450 mA 800 mA 100 Freescale Semiconductor ...
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... NVCC_GPIO NVCC_JTAG NVCC_KPAD NVCC_LCD NVCC_LVDS NVCC_LVDS_BG NVCC_NANDF NVCC_PATA NVCC_REST NVCC_SD1 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Conditions Max Current Fuse Write Mode operation 1.8v (DDR2) 1.5v (DDR3) 1.2v (LPDDR2) Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq ...
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... Automotive and Infotainment Applications Processors, Rev Conditions Max Current Use maximal IO Eq Use maximal IO Eq Conditions Typical at 25 °C RX 5.5 Full Speed High Speed 6.5 Full Speed TX 6 High Speed Full Speed High Speed TX 8 Unit N=2 Max Unit — — mA — — Freescale Semiconductor ...
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... ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor NOTE Electrical Characteristics 25 ...
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... If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable. i.MX53xA Automotive and Infotainment Applications Processors, Rev 90% 90% Δt > 0 90% Δt > 0 Δt > 0 Δt > 0 90% Δt > 0 90% Figure 2. Power Up Detailed Sequence NOTE 90% 90% Δt > 0 Δt > 0 90% Δt > 0 90% Δt > Freescale Semiconductor ...
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... Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes • Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 6 Ultra High voltage I/O (UHVIO) supplies , Electrical Characteristics . A deviation of few ) Section 6, ...
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... Table 6, unless otherwise noted. Min Typ Max OVDD – 0.15 — — 0.8*OVDD — — 0.15 × 0.2 OVDD –0.85 –1.7 — — –2.5 –3.4 0.9 1.9 — — 2.9 3.8 –2.1 –4.2 — — –6.3 –8.4 Freescale Semiconductor Unit ...
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... DDR2 Mode I/O DC Parameters The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11 are guaranteed per the operating ranges in i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Test Conditions × Iol Vout = 0.2 ...
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... OVDD+0.3 –0.3 — Vref-0.125V –0.3 — OVDD+0.3 0.25 — OVDD+0.6 Vref Vref + 0.04 — — 1 — — — 130 — 1 Min Typ Max — — — — 0.1*OVDD 0.5*OVDD 0.51*OVDD — OVDD — Vref-0.13V Freescale Semiconductor Unit μA kΩ Unit ...
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... Keeper Circuit Resistance 1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3) 2 external reference voltage Vref – DDR3 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Vih(diff) Vil(diff) Iin Vin = 0 V Vin=OVDD — — Table 13. DDR3 I/O DC Electrical Parameters ...
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... OVDD 0 — 0.35 0.62 — 1.27 0.5 × OVDD — — 0.5 × OVDD — — — — 1 — — 161 1 — — — — — — — 130 — Freescale Semiconductor Unit μA μA μA μA μA kΩ ...
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... Input current (22 kΩ Pull-up) Input current (75 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (360 kΩ Pull-down) Keeper Circuit Resistance i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Test Conditions Voh Iout = –1mA OVDD–0.15 Iout= specified Ioh ...
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... Automotive and Infotainment Applications Processors, Rev Symbol Test Conditions V Rload=100Ω OD padP, –padN 1.125 OS NOTE Min Typ Max 250 350 450 1.25 1.375 1.6 0.9 1.025 1.25 1.2 1.375 Figure 4). Freescale Semiconductor Unit mV V ...
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... OVDD Vref1 Vref 0 Vovdd – Vref1 Rpu = Rpd = Vovdd – Vref2 Figure 4. Impedance Matching Load for Measurement i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × ...
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... The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. i.MX53xA Automotive and Infotainment Applications Processors, Rev Table 17. GPIO Output Buffer Impedance Test Conditions Min Typ Max OVDD 2.775 V OVDD 1.875 V 104 150 250 52 75 125 134 243 44 66 122 Freescale Semiconductor Unit Ω Ω ...
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... If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference resistor value must be 160 Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory devices should be kept to 240 Ω per the JEDEC standard. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Drive strength (DSE) 000 001 ...
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... Figure 5. Load Circuit for Output 80% 20% tr Figure 6. Output Transition Time Waveform Typ Max OVDD OVDD OVDD OVDD 1.875 V 3.3 V 1.65 V 3.6 V 114 124 135 198 118 126 154 179 Figure 5 and Figure 6. OVDD 80% 20 Freescale Semiconductor Unit 206 Ω 103 69 217 Ω 109 72 ...
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... Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 21. GPIO I/O AC Parameters Fast Mode Parameter Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Test Condition tr tr ...
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... Max Vref+0.25 — — Vref-0.25 — — 0.5 — OVDD Vref 0.175 – — Vref + 0.175 Vref 0.125 – — Vref + 0.125 0.4 — 2 — — 0.2 0.1 Freescale Semiconductor Unit ns V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns Unit V/ns ns ...
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... AC parameters for LPDDR2 I/O operating in DDR3 mode. Table 24. LPDDR2 I/O DDR3 mode AC Characteristics Parameter AC input logic high AC input logic low 2 AC differential input voltage Input AC differential cross point voltage i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Test Condition Vih(ac) — Vil(ac) — Vidh(ac) — ...
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... Vref Vox(ac) — Ω to Vref tsr t clk=266MHz SKD clk=400MHz Symbol Test Condition trm — 1 (continued) Min Typ Max 0.15 – — Vref + 0.15 2.5 — 5 — — 0.2 0.1 Table 25 and Min Typ Max — — 25 Freescale Semiconductor Unit V V/ns ns Unit ns ...
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... Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) Parameter Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Test Symbol Condition trm — ...
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... Min Typ Max 0.26 — 0.5 0.26 — 0.5 — 300 — — — 150 Freescale Semiconductor Unit V/ns mA/ns ns Unit ns MHz mV ...
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... Clock Amplifier Parameters (CKIH1, CKIH2) The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 30 lists the timing parameters. CC1 Figure 8 ...
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... Table 32. Freescale Semiconductor V V Unit MHz MHz MHz — — — — pdref d µ dck ns mW ...
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... MHz (that is ns) guaranties a proper operation for devices having t NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with 33.33 MHz clock. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Figure 11, Figure 12, Figure 13, ...
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... Automotive and Infotainment Applications Processors, Rev (RE_B high to output high-Z). In most devices, the rhz NF1 NF3 NF5 NF8 NF9 command Figure 10. Command Latch Cycle Timing NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 11. Address Latch Cycle Timing NF2 NF4 Freescale Semiconductor ...
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... Figure 13. Read Data Latch Timing, Asymmetric Mode NFCE_B NFRE_B NFRB_B NF12 NFIO[15:0] Figure 14. Read Data Latch Timing, Symmetric Mode i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor NF3 NF10 NF11 NF5 NF8 NF9 Data to NF Figure 12. Write Data Latch Timing ...
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... Electrical Characteristics NFCLE NFCE_B NFWE_B NFRE_B NFRB_B i.MX53xA Automotive and Infotainment Applications Processors, Rev NF19 NF20 NF21 NF22 Figure 15. Other Timing Parameters Freescale Semiconductor ...
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... T “emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 35. NFC—Timing Characteristics Symbol Asymmetric Mode Min ...
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... IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[25:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode) EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT ) is Data propogation delay from I/O pad to Dpd Table 37 provides EIM interface Freescale Semiconductor ...
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... For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map. 2 NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0] 3 NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8] i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 37. EIM Internal Module Multiplexing 16 Bit MUM = 0, MUM = 0, MUM = 0, ...
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... WE18 WE19 WE20 WE21 Figure 17. EIM Inputs Timing Diagram Table 38. EIM Bus Timing Parameters BCD = 0 BCD = 1 Max Min Max 2*t 0.8*t ... WE3 WE5 WE7 WE9 WE11 WE13 WE15 WE17 1 BCD = 2 BCD = 3 Min Max Min 3*t 4*t 1.2*t 1.6*t Freescale Semiconductor Max ...
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... WE19 Input Data hold 2 time from Clock rise WE20 WAIT_B setup 2 time to Clock rise WE21 WAIT_B hold time 2 from Clock rise i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor BCD = 0 BCD = 1 Max Min Max 0.8*t -0.5*t+1.75 -t-1.25 -t+1.75 0.5*t+1.75 t-1.25 t+1 ...
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... WE_B ADV_B OE_B BEy_B DATA Figure 18. Synchronous Memory Read Access, WSC=1 i.MX53xA Automotive and Infotainment Applications Processors, Rev ≤ 104 MHz. If BCD = 1, then 133 MHz is WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 D(v1) WE5 WE7 WE11 WE13 WE19 Freescale Semiconductor ...
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... OE_B BEy_B Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor WE4 Address V1 WE6 WE8 WE14 WE15 ...
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... RWSC, OEN, and CSN is configured differently. Refer to i.MX53xA RM for the EIM programming model. i.MX53xA Automotive and Infotainment Applications Processors, Rev WE4 WE5 Address V1 WE6 WE15 WE10 WE12 Table 39 help to determine timing parameters relative to the chip select WE19 Data WE18 WE7 WE11 WE13 Figure 22 through Freescale Semiconductor ...
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... Figure 22. Asynchronous Memory Read Access (RWSC = 5) INT_CLK MAXCSO CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B MAXCO Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access ...
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... Figure 25. Asynchronous A/D Muxed Write Access i.MX53xA Automotive and Infotainment Applications Processors, Rev WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr. V1 WE32A WE33 WE40A WE39 WE45 WE32 Next Address WE34 WE40 WE46 WE42 WE42 WE34 WE46 WE42 Freescale Semiconductor ...
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... OE_B BEy_B DATA[7:0] DTACK CSx_B ADDR Last Valid Address WE_B ADV_B OE_B BEy_B DATA DTACK i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 WE47 Figure 26. DTACK Read Access (DAP=0) WE31 Address V1 WE33 WE39 ...
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... CSN — — (WEA - CSA) — (WEN_CSN) — (OEA - CSA (OEA + RADVN+RADVA+A DH+1-CSA) — (OEN - CSN) 6 — (RBEA - CSA) 7 — (RBEN - CSN) — (ADVA - CSA) — CSN 3 + (ADVN + ADVA + 1 - CSA) — WCSA — (WADVN + WADVA + ADH + 1 - WCSA) — CSN Freescale Semiconductor ...
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... CS Negation. This bit field determines when CS signal is negated during read/write cycles axi_clk cycle time Assertion. This bit field determines when BE signal is asserted during read cycles Negation. This bit field determines when BE signal is negated during read cycles. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Determination by Synchronous measured 12 parameters ...
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... Table 40. DDR SDRAM Timing Parameter Table ID Parameter DDR1 SDRAM clock high-level width DDR2 SDRAM clock low-level width i.MX53xA Automotive and Infotainment Applications Processors, Rev DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Symbol DDR1 DDR2 1 2 SDCLK = 400 MHz Units Min Max 0.48 0. 0.48 0. Freescale Semiconductor ...
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... LP4 CS, CKE hold time LP3 CA setup time LP4 CA hold time 1 All timings are refer to Vref level cross point. 2 Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol LP4 ...
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... Figure 30. DDR SDRAM Data Write Cycle Table 42. DDR SDRAM Write Cycle Parameter DDR23 DDR18 Data Data Data Data DDR18 SDCLK = 400 MHz Symbol Min Max t 0.285 — 0.285 — -0.25 +0.25 DQSS t 0.45 0.55 DQSH t 0.45 0.55 DQSL Freescale Semiconductor Unit ns ns tCK tCK tCK ...
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... This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI modules and the respective routing of these signals is shown in i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor DATA DATA DATA ...
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... DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC Table 45 CS2 CS3 CS2 CS3 Symbol t clk RISE/FALL t CSLH t SCS t HCS t PDmosi t Smiso I/O Access lists the CSPI master mode timing CS6 CS5 CS4 Min Max 60 — 26 — — — 26 — 26 — 26 — – — Freescale Semiconductor Unit ...
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... SSx pulse width CS5 SSx Lead Time (CS setup time) CS6 SSx Lag Time (CS hold time) CS7 MOSI Propagation Delay (C CS8 MISO Setup Time i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Min t 5 Hmiso t 5 SDRY Parameters” CS2 ...
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... T c − 9.0 — — Min Max 0 — 5 — Min Max 15 — — 20 Half SCLK period — 5 — 5 — 4 — 4 — Min Max Condition 4 × 30.0 — × 30.0 — — — 2 × — — Freescale Semiconductor Unit ns ns Unit Unit ns ns ...
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... SCKT rising edge to FST out (wr) low 82 SCKT rising edge to FST out (wl) high 83 SCKT rising edge to FST out (wl) low 84 SCKT rising edge to data out enable from high impedance i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor 1 2,3 ’ Symbol Expression 2 × − 9.0 — — ...
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... Max Condition — — 18 — — 13 — — 21 — — 16 — 2.0 — — 18.0 — — 2.0 — — 18.0 — — 4.0 — — 5.0 — — — C — — 18.0 — — — 18.0 — Freescale Semiconductor 4 Unit ...
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... SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor First Bit Figure 34. ESAI Transmitter Timing Electrical Characteristics 83 87 Last Bit 91 73 ...
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... Electrical Characteristics SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX53xA Automotive and Infotainment Applications Processors, Rev First Bit Figure 35. ESAI Receiver Timing 70 72 Last Bit 75 Freescale Semiconductor ...
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... SD5 Clock Fall Time eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC Output Delay eSDHC Input/Card Outputs CMD, DAT (Reference to CLK) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 49 lists the SD/eMMC4.3 timing characteristics. SD4 SD2 SD5 SCK ...
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... SD3 SD4 DAT0 DAT1 ...... DAT7 Figure 37. eMMC4.4 Timing Symbols Card Input Clock Symbols Min Max t 2.5 — ISU t 2.5 — IH – 25 MHz. In high-speed mode, – 20 MHz. In high-speed mode, clock SD1 SD2 ...... ...... Min Max 0 52 –5 5 Freescale Semiconductor Unit ns ns Unit MHz ns ...
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... M4 FEC_RX_CLK pulse width low 1 FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbols t ISU t IH Table 51 lists the MII receive channel signal timing Table 51 ...
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... FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. i.MX53xA Automotive and Infotainment Applications Processors, Rev Figure 39 Table 52. Table 52. MII Transmit Signal Timing 1 2 Characteristic M4 shows MII transmit signal timing Min Max Unit 5 — ns — 35% 65% FEC_TX_CLK period 35% 65% FEC_TX_CLK period Freescale Semiconductor ...
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... M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) M12 FEC_MDIO (input) to FEC_MDC rising edge setup i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 53. MII Async Inputs Signal Timing ...
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... Automotive and Infotainment Applications Processors, Rev Characteristics M14 M12 M13 Table 55 and Figure 42. Table 55. RMII Signal Timing 1 Characteristics Min Max Unit 0 — 60% FEC_MDC period % 40 60% FEC_MDC period % M15 M10 M11 Min Max Unit 35% 65% REF_CLK period 35% 65% REF_CLK period 2 — ns — Freescale Semiconductor ...
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... I/O pins. See the IOMUXC chapter of the i.MX53 Reference Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 55. RMII Signal Timing (continued) 1 Characteristics ...
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... Freescale Semiconductor 2 C START Unit Max µ — s µ — s µ — µ 0.9 s µ — s µ — s µ — ...
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... CSIx_DAT18 G[1], R[3] R[3],G[4],B[3] CSIx_DAT19 G[2], R[4] R[4],G[5],B[4] 1 CSIx stands for CSI1 or CSI2 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor cameras, displays, graphics accelerators, and TV encoders. — Table 57 defines the mapping of the Sensor Interface 2 3 RGB666 ...
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... Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. i.MX53xA Automotive and Infotainment Applications Processors, Rev Active Line n+1th frame invalid 1st byte 1st byte Freescale Semiconductor ...
Page 85
... SENSB_PIX_CLK (Sensor Output) SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Section 4.7.8.2.2, “Gated Clock n+1th frame 1st byte is that of a typical sensor. Some other sensors may have a slightly IP2 IP3 Figure 46 ...
Page 86
... The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX53xA Automotive and Infotainment Applications Processors, Rev Symbol Min Fpck 0.01 Tsu 2 Thd 1 Table 59 defines the mapping of the Display Max Unit 180 MHz — ns — ns Freescale Semiconductor ...
Page 87
... DISPx_DAT17 DAT[17] — DISPx_DAT18 DAT[18] — DISPx_DAT19 DAT[19] — DISPx_DAT20 DAT[20] — DISPx_DAT21 DAT[21] — i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 59. Video Signal Cross-Reference LCD 24 Bit 8-bit 16-bit 20-bit 2 RGB RGB YCrCb YCrCb YCrCb B[0] B[0] Y/C[0] ...
Page 88
... CS0 — CS1 Alternate mode of PWM output for contrast or brightness control WR — RD — RS1 Register select signal RS2 Optional RS2 DRDY Data validation/blank, data enable — Additional data synchronous signals with programmable — features/timing Freescale Semiconductor ...
Page 89
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor NOTE NOTE Electrical Characteristics 89 ...
Page 90
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX53xA Automotive and Infotainment Applications Processors, Rev LINE 2 LINE 3 LINE LINE n-1 LINE n m–1 m Freescale Semiconductor ...
Page 91
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 ...
Page 92
... Tvbi1 BGYP Tsw BGYP—width of first Vertical blanking interval in line.The BGYP should be built by suitable DI’s counter. Tvbi2 (SCREEN_HEIGHT – Width of second Vertical × BGYP – FH) Tsw blanking interval in line.The FH should be built by suitable DI’s counter. and Figure 49. Description Unit ns IPP_DISP_CLK Freescale Semiconductor ...
Page 93
... Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH. The maximal accuracy of UP/DOWN edge of controls is: i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Value Todicp DISP_CLK_OFFSET × ...
Page 94
... Tdicd Tdicp–Tdicd+Tdicu–1.24 Tdicp–Tdicd+Tdicu Tdicd–1.24 Tdicu Tdicp–Tdicd–1.24 Tdicp–Tdicu Tocsu–1.24 Tocsu Tdicd–1.24–Tocsu%Tdicp Tdicu lists the synchronous display interface 1 Typ Max 2 3 –Tdicu Tdicd–Tdicu+1.24 Tdicp–Tdicd+Tdicu+1.2 — — Tocsu+1.24 — Freescale Semiconductor Unit ...
Page 95
... VSYNC and HSYNC coincide transition even field (of the same frame), they do not — coincide. • The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor × ⎛ 2 DISP_CLK_DOWN 1 × ---------------------------------------------------------- - ...
Page 96
... Odd Field Line and Field Timing - NTSC 623 624 625 1 310 311 312 313 Line and Field Timing - PAL Odd Field 267 268 269 273 Even Field Odd Field 314 315 316 336 Even Field Freescale Semiconductor ...
Page 97
... Hue Accuracy Color Saturation Accuracy Chroma AM Noise Chroma PM Noise Chroma Nonlinear Phase Chroma Nonlinear Gain Chroma/Luma Intermodulation Chroma/Luma Gain Inequality i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 62. All the parameters in the table are defined Conditions — — — — 1.05 kΩ ...
Page 98
... MHz 0-15 MHz 55. The timing images correspond to active-low IPP_CS, WR and RD Min Typ Max Unit — 1.0 — ±ns –0.2 — 0.2 dB –0.2 — 0.2 dB — 3.2 — % — 3.4 — % — 62 — dB — 72 — dB Figure Freescale Semiconductor 52, ...
Page 99
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Burst access mode with sampling by CS signal Electrical Characteristics ...
Page 100
... Burst access mode with sampling by WR/RD signals IPP_CS IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 100 Freescale Semiconductor ...
Page 101
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Burst access mode with sampling by CS signal Electrical Characteristics ...
Page 102
... DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 102 Burst access mode with sampling by ENABLE signal Freescale Semiconductor ...
Page 103
... Table 64 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor waiting Electrical Characteristics waiting 103 ...
Page 104
... IP27 IP37 IP38 Description predefined value in DI REGISTER predefined value in DI REGISTER RS strobe switch, predefined value in DI REGISTER CS strobe switch, predefined value in DI REGISTER CS strobe release, predefined value in DI REGISTER RS strobe release, predefined value in DI REGISTER Freescale Semiconductor Unit — — ...
Page 105
... Display control down for CS Tdicdcs DISP_DOWN is predefined in REGISTER. 4 Display control up for CS DISP_UP is predefined in REGISTER. 5 Display control down for RS DISP_DOWN is predefined in REGISTER. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Value Tdcsw UP# Tdchw DOWN# Min Tdicpw – 1.24 Tdicpw Tdicurs – 1.24 Tdicurs Tdicucs – ...
Page 106
... Automotive and Infotainment Applications Processors, Rev. 3 106 × ⎛ 2 DISP_UP_# 1 × --------------------------------------------- - Tdicurs = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_UP_# 1 × --------------------------------------------- - Tdicuw = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ Table 65 and Table 66 lists the Freescale Semiconductor ...
Page 107
... Table 65. MLB 256/512 Fs Timing Parameters Parameter Symbol 1 MLBCLK operating frequency f MLBCLK rise time t MLB fall time t MLBCLK cycle time t mckc i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Figure 58. MediaLB Timing Min Typ Max 11.264 mck 12.288 24.576 24.6272 25.600 — — mckr — ...
Page 108
... Note — ns — — ns — ns — mckl — ns Note Max Units Comment MHz Min: 1024*fs at 44.0 kHz Typ: 1024*fs at 48.0 kHz Max: 1024fs*fs at 48.1 kHz Max: 1024*fs PLL unlocked — ns — — ns PLL unlocked — ns — PLL unlocked 0 Note Freescale Semiconductor ...
Page 109
... Reset Time Low OW2 Presence Detect High OW3 Presence Detect Low OW4 Reset Time High (includes recovery time order not to mask signaling by other devices on the 1-Wire bus, t i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Min Typ Max 1 — 0 — 0 — t ...
Page 110
... OW6 OW5 Symbol t LOW0 t SLOT t REC Figure 63 depicts the Read Sequence timing, and OW8 OW8 OW11 OW9 OW10 Figure 63. Read Sequence Timing Diagram t REC Min Typ Max 60 100 120 OW5 117 120 1 — — Table 69 Freescale Semiconductor Unit µs µs µs ...
Page 111
... System CLK frequency 2a Clock high time 2b Clock low time 3a Clock fall time 3b Clock rise time 4a Output delay time 4b Output setup time PWMO = 30 pF i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 69. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT LOWR t RDV t RELEASE Table 70 lists the PWM timing parameters ...
Page 112
... Automotive and Infotainment Applications Processors, Rev. 3 112 SI2 Parameter 1 1 – where all signals have the same capacitive load value. SI1 Symbol Min Max S — 1.25 rise S — 1.25 fall C — 20 host Freescale Semiconductor Unit V/ns V/ns pF ...
Page 113
... Max difference in cable propagation delay without accounting for ground bounce 1 Values provided where applicable. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 72. PATA Timing Parameters Description UDMA2, UDMA3 UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Electrical Characteristics ...
Page 114
... Automotive and Infotainment Applications Processors, Rev. 3 114 Table 73 lists the timing parameters for PIO read. Figure 66. PIO Read Timing Diagram Table 73. PIO Read Timing Parameters Value Controlling Variable time_1 time_2r time_9 time_2 (affects tsu and tco) — time_ax time_pio_rdx time_1, time_2r, time_9 Freescale Semiconductor ...
Page 115
... Avoid bus contention when switching buffer on by making ton long enough — — Avoid bus contention when switching buffer off by making toff long enough i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 74 lists the timing parameters for PIO write. Figure 67. Multi-word DMA (MDMA) Timing Table 74. PIO Write Timing Parameters ...
Page 116
... MDMA write, and Figure 68. MDMA Read Timing Diagram Figure 69. MDMA Write Timing Diagram Value × T – (tsu + tco + 2 Table 75 lists Controlling Variable time_m time_d time_k time_d, time_k time_d — time_d time_k × × tbuf + 2 tcable2) time_d, 2 time_k Freescale Semiconductor ...
Page 117
... UDMA in transfer starts, host terminates transfer, Figure 72 Table 76 lists the timing parameters for UDMA in burst. Figure 70. UDMA in Transfer Starts Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Value × T – tskew1 × T – tskew1 and Figure 69) equals (tk – ...
Page 118
... Automotive and Infotainment Applications Processors, Rev. 3 118 Table 76. UDMA in Burst Timing Parameters Description × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) Controlling Variable time_ack time_env tskew3, ti_ds, ti_dh should be low enough Freescale Semiconductor ...
Page 119
... UDMA out transfer starts, host terminates transfer, Figure 75 Table 77 lists the timing parameters for UDMA out burst. Figure 73. UDMA Out Transfer Starts Timing Diagram i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Description × T – (tskew1 + tskew2 + tskew6) × × × ...
Page 120
... Automotive and Infotainment Applications Processors, Rev. 3 120 Value × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T – (tskew1 + tskew2) × × Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc Freescale Semiconductor ...
Page 121
... Parameters Differential peak voltage (typically 0.71 V) Common mode voltage (refclk_p + refclk_m Total phase jitter Minimum/maximum duty cycle Frequency range i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Value × tsui + tco + tbuf + tbuf × T – (tskew1) × T – (tskew1 + tskew2) × ...
Page 122
... Table 79. SATA2 PHY Transmitter Characteristics Parameters Transmit common mode voltage Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 122 NOTE Symbol Min V 0.4 CTM — –0.5 Figure 76. The square Typ Max Unit — 0.6 V — 0.5 dB Freescale Semiconductor ...
Page 123
... The reference clock input frequency must fall within the specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Min — ...
Page 124
... Automotive and Infotainment Applications Processors, Rev. 3 124 Figure 78 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 77. Test Clock Input Timing Diagram SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid Table 81. SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...
Page 125
... Boundary scan input data hold time SJ6 TCK low to output data valid SJ7 TCK low to output high impedance SJ8 TMS, TDI data set-up time i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 80 ...
Page 126
... Max 25 — ns — — 100 — — ns Timing Parameter Range Units Min Max — 0.7 ns — 1.5 ns — 24.2 — 31.3 ns — 1.5 — 13.6 — 18.0 40.0 — ns 16.0 — ns 16.0 — ns 40.0 — ns 16.0 — ns 16.0 — ns Freescale Semiconductor ...
Page 127
... The SSI timing diagrams use generic signal names wherein the names used in the i.MX53 Reference Manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor srckp srckpl srckph V ...
Page 128
... Internal Clock Operation lists the timing parameters for the SS3 SS12 SS15 SS18 SS19 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns Freescale Semiconductor ...
Page 129
... Transmit and Receive sections of the SSI. • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Parameter Synchronous Internal Clock Operation NOTE Electrical Characteristics ...
Page 130
... Parameter Internal Clock Operation lists the timing parameters for the SS3 SS13 SS21 SS49 Min Max 81.4 — 36.0 — — 6.0 36.0 — — 6.0 — 15.0 — 15.0 — 15.0 — 15.0 10.0 — 0.0 — Freescale Semiconductor Unit ...
Page 131
... The terms WL and BL refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Parameter Oversampling Clock Operation NOTE Electrical Characteristics ...
Page 132
... External Clock Operation lists the timing parameters for SS24 SS33 SS39 SS38 SS45 SS46 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns Freescale Semiconductor ...
Page 133
... The terms WL and BL refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Parameter Synchronous External Clock Operation NOTE Electrical Characteristics ...
Page 134
... SS25 SS28 SS30 SS32 SS35 SS40 Parameter External Clock Operation lists the timing parameters for the SS24 SS34 SS41 SS36 Min Max Unit 81.4 — — ns — 6 — ns — 6.0 ns –10 15 — ns –10 15 — ns — 6.0 ns — 6 — — ns Freescale Semiconductor ...
Page 135
... UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 89 lists the UART RS-232 serial mode transmit timing characteristics. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor NOTE Table 88 shows the UART I/O configuration based on the Table 88 ...
Page 136
... UA1 UA1 Min Max 1 – 1/F + baud_rate 2 T ref_clk ref_clk Table 90 Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA2 UA2 Min Max 2 – 1/F + baud_rate ) 1/(16*F ) baud_rate baud_rate Table 91 Freescale Semiconductor Units — lists Units — lists ...
Page 137
... The UART receiver can tolerate 1/(16*F exceed 3/(16*F ). baud_rate Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. baud_rate i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor UA3 Bit 1 Bit 2 Bit 3 Bit 4 Symbol t TIRbit t (3/16)*(1/F ...
Page 138
... Automotive and Infotainment Applications Processors, Rev. 3 138 Parameters.” Direction Transmit enable, active low TX data when USB_TXOE_B is low Differential RX data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 RX indicator when USB_TXOE_B is high US1 US4 Signal Description US3 US2 Freescale Semiconductor ...
Page 139
... US2 TX Rise/Fall Time USB_SE0_VM US3 TX Rise/Fall Time USB_TXOE_B US4 TX Duty Cycle US7 RX Rise/Fall Time US8 RX Rise/Fall Time USB_SE0_VM i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor US7 Signal Name Direction Min USB_DAT_VP Out -— Out — Out — USB_DAT_VP Out 49 ...
Page 140
... Automotive and Infotainment Applications Processors, Rev. 3 140 Direction Out Transmit enable, active low Out TX data when USB_TXOE_B is low Out SE0 drive when USB_TXOE_B is low In Buffered data on DP when USB_TXOE_B is high In Buffered data on DM when USB_TXOE_B is high US9 US12 Signal Description US11 US10 Freescale Semiconductor ...
Page 141
... USB_DAT_VP US10 TX Rise/Fall Time USB_SE0_VM US11 TX Rise/Fall Time USB_TXOE_B US12 TX Duty Cycle USB_DAT_VP US15 RX Rise/Fall Time US16 RX Rise/Fall Time i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor US15 Signal Min Source Out — Out — Out — Out 49.0 USB_VP1 In — ...
Page 142
... Automotive and Infotainment Applications Processors, Rev. 3 142 Direction Out Transmit enable, active low Out (Tx data when USB_TXOE_B is low In (Rx data when USB_TXOE_B is high Out (Tx data when USB_TXOE_B low In (Rx data when USB_TXOE_B high US18 US22 US26 US28 Signal Description US20 US19 US22 US27 Freescale Semiconductor ...
Page 143
... US19 TX Rise/Fall Time US20 TX Rise/Fall Time US21 TX Duty Cycle US22 TX Overlap US26 RX Rise/Fall Time US27 RX Rise/Fall Time US28 RX Skew i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Signal Name Direction Min USB_DAT_V Out — P USB_SE0_V Out — M USB_TXOE Out — ...
Page 144
... Automotive and Infotainment Applications Processors, Rev. 3 144 Direction Out Transmit enable, active low Out TX VP data when USB_TXOE_B is low Out TX VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high US30 US34 Signal Description US32 US31 Freescale Semiconductor ...
Page 145
... US31 TX Rise/Fall Time US32 TX Rise/Fall Time US33 TX Duty Cycle US34 TX Overlap US38 RX Rise/Fall Time US39 RX Rise/Fall Time US40 RX Skew i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor US38 US40 US39 Signal Direction Min USB_DAT_VP Out — USB_SE0_V Out — M USB_TXOE_ Out — ...
Page 146
... Stop. The link asserts this signal for 1 clock cycle to stop the Out data stream currently on the bus. In Next. The PHY asserts this signal to throttle the data. US16 US16 US17 Parameter Signal Description US17 Conditions / Min Max Unit Reference Signal 6.0 — 0.0 — — 9 Freescale Semiconductor ...
Page 147
... Reference Clock frequency 24 MHz Rise/fall time — Jitter (peak-peak) < 1.2 MHz Jitter (peak-peak) > 1.2 MHz Duty-cycle Reference Clock frequency 24 MHz i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Table 103. USB PHY AC Timing Parameters Min Typ 75 — 4 0.5 75 — 4 0.5 — ...
Page 148
... Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — 4.4 Ω ±10% (steady state). No external resistors required. Typ 24 Typ 1 -- 32.768/32.0 Typ Max Unit 1.4 2.0 V 1.4 4.0 V 0.45 0.8 V 4.6 4.75 V Max Units 27 MHz Max Units -- kHz Freescale Semiconductor ...
Page 149
... Fuse Map document and Boot chapter in i.MX53 Reference Manual. Table 110. Fuses and Associated Pins Used for Boot Direction at Pin Reset BOOT_MODE[1] Input BOOT_MODE[0] Input i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Symbol Min V 1.15 VID_DIG_PLL V 1.7 VDD_ANA_PLL — ...
Page 150
... BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses. Comment Only SS1 is supported Only SS1 is supported Only SS1 is supported Freescale Semiconductor ...
Page 151
... By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to achieve the standard operating mode (see VDD_DIG_PLL on should be configured by software by boot code after power-up to 1.3 V output. This is done by programming the PLL1P2_VREG bits. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Allocated Pads During Boot Table Boot Mode Configuration Comment • ...
Page 152
... Automotive and Infotainment Applications Processors, Rev. 3 152 Figure 101 Figure 102 Figure 100 Package Top View shows the bottom view and the ball shows the side view of the 19×19 Freescale Semiconductor ...
Page 153
... Figure 101 Package, 529 Solder Balls, Bottom View i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Figure 102 Package Side View Package Information and Contact Assignments 153 ...
Page 154
... NVCC_JTAG G9 NVCC_KEYPAD F7 NVCC_LCD J6, J7 NVCC_LVDS U13 NVCC_LVDS_BG U14 NVCC_NANDF T12 NVCC_PATA N7 NVCC_RESET H16 NVCC_SD1 H15 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 154 100, Figure 101, and Figure 102. Table 114 shows the package ball map. Package Contact Assignment(s) Freescale Semiconductor ...
Page 155
... A15, B15 VPH A9, B9 Table 113 displays an alpha-sorted list of the signal assignments including power rails. The table also includes out of reset pad state. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Package Contact Assignment(s) 155 ...
Page 156
... Input 360 KΩ PD Input 360 KΩ PD Input 360 KΩ PD Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 157
... NVCC_LCD DISP0_DAT5 H3 NVCC_LCD DISP0_DAT6 G1 NVCC_LCD DISP0_DAT7 H6 NVCC_LCD DISP0_DAT8 G6 NVCC_LCD i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT1 GPIO-4 gpio4_GPIO[16] GPIO ALT1 GPIO-4 gpio4_GPIO[17] ...
Page 158
... Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Input — Output High Output High Output High Freescale Semiconductor ...
Page 159
... U22 NVCC_EMI_DRAM DRAM_D23 R23 NVCC_EMI_DRAM DRAM_D24 Y20 NVCC_EMI_DRAM DRAM_D25 W21 NVCC_EMI_DRAM i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_D[0] DDR3 ALT0 ...
Page 160
... High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output Low Output Low Output Low Output Low Output High Output Low Output Low Output Low Freescale Semiconductor ...
Page 161
... DRAM_SDQS Y22 NVCC_EMI_DRAM 3 DRAM_SDQS Y23 NVCC_EMI_DRAM 3_B DRAM_SDWE L19 NVCC_EMI_DRAM i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_SDB A[2] DDR3 ...
Page 162
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 163
... AC5 NVCC_EIM_MAIN EIM_DA8 AA8 NVCC_EIM_MAIN EIM_DA9 W10 NVCC_EIM_MAIN EIM_EB0 AC3 NVCC_EIM_MAIN i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-3 gpio3_GPIO[30] UHVIO ALT1 ...
Page 164
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 165
... NVCC_KEYPAD KEY_COL4 E5 NVCC_KEYPAD KEY_ROW0 B3 NVCC_KEYPAD KEY_ROW1 D6 NVCC_KEYPAD KEY_ROW2 D5 NVCC_KEYPAD i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT0 GPIO-4 gpio4_GPIO[3] GPIO ALT0 GPIO-4 gpio4_GPIO[4] ...
Page 166
... KΩ PD — — Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Freescale Semiconductor ...
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... NVCC_PATA PATA_DATA11 M6 NVCC_PATA PATA_DATA12 N5 NVCC_PATA PATA_DATA13 N6 NVCC_PATA PATA_DATA14 P6 NVCC_PATA PATA_DATA15 P5 NVCC_PATA i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode LVDS ALT0 GPIO-6 gpio6_GPI[23] LVDS ALT0 ...
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... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Output — Output — Input 100 KΩ PU Input 100 KΩ PU — — — — — — — — — — — — — — Freescale Semiconductor ...
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... B TVDAC_IOR AC21 TVDAC_AHVDDRG B TVDAC_VREF Y18 TVDAC_AHVDDRG B USB_H1_DN B17 USB_H1_VDDA25, USB_H1_VDDA33 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-1 gpio1_GPIO[20] UHVIO ALT1 GPIO-1 gpio1_GPIO[18] ...
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... ANALOG — XTALO XTAL SC Section 5.1, “Boot Mode Configuration Pins” NOTE 1 Config./ Direction Value — — — — — — — — — — — — — — — — — — — — — — for details. Freescale Semiconductor ...
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... Pitch Ball Map shows the 19 × 19 mm, 0.8 pitch ball map. Table 114 i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Table 114 mm, 0.8 Pitch Ball Map 171 ...
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... Package Information and Contact Assignments i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 172 Table 114 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
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... Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Table 114 mm, 0.8 Pitch Ball Map 173 ...
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... Package Information and Contact Assignments i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 174 Table 114 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
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... Updated Table 102, "USB Timing Specification for Normal ULPI Mode," on page • Updated the second footnote on on page 156. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor Substantive Change(s) updated the caution note on 3. page 6 in Section 1.2, “ ...
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... MHz from 1.0/1.05/1.1 to 1.05/1.1/1.15 V minimum/nominal/maximum. — Stop mode from 0.9/0.95/1.1 to 0.8/0.85/1.15 V minimum/nominal/maximum. • Added statements to footnotes 4 and 5. Rev 0 02/2011 Initial release. i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 176 Substantive Change(s) Section 3.1, “Special Signal Considerations.” 20. Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3 Freescale Semiconductor 177 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...