MCIMX534AVV8C Freescale Semiconductor, MCIMX534AVV8C Datasheet - Page 175

• Manufacturer Part Number: MCIMX534AVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX534AVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 800MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 0.8V To 1.15V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7
Table 115
Freescale Semiconductor
Number
Rev 3
Rev 2
Rev.
Revision History
06/2011 In
05/2011 • Updated
provides a revision history for this data sheet.
Date
• Updated the note on
• Modified VDD_FUSE design best practice footnote on
• Changed VDD_FUSE max current to 120 mA in
• In
• Made changes related to text, tables, and figures in
• Removed the Standard Serial Interfaces section.
• In
• In
• In
• In
• Updated keeper values in
• Fixed titles of
• Updated
• Added
• Added
• Deleted the second footnote of
• Deleted the Revision 1.0 EIM Internal Module Multiplexing table.
• Deleted the CKIL Electrical Specifications table.
• Deleted the CSPI Slave Mode Timing Parameters table .
• Changed the title of
• Updated the last paragragh of
• Updated
• Removed the “Differential pulse skew
• Updated
• Updated
• Updated
• Updated the second footnote on
Section 4.1.1, “Absolute Maximum Ratings,”
page
specification.
(DDR2/LVDDR2, LPDDR2, and
ACCZ test results, and changing note about DDR load model.
pull-up/down from 250/120 nA to 2 μA, all input currents with pull-up from 0.12 μΑ to 2 μA when Vin =
OVDD, and input current with pull-down from 0.25 μA to 2 μA when Vin = 0.
pull-up/down from 250/120 nA to 1 μA, all input currents with pull-up from 0.12 μΑ to 1 μA when Vin =
OVDD, and input current with pull-down from 0.25 μA to 1 μA when Vin = 0.
pull-up/down from 300/63 nA to 1 μA, all input currents with pull-up from 0.06 μΑ to 1 μA when Vin =
OVDD, and input current with pull-down from 0.3 μA to 1 μA when Vin = 0.
Output Buffer Impedance.”
on page 44
on page
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 3
Table 9, "USB Interface Current Consumption," on page
Table 10, "GPIO I/O DC Electrical Characteristics," on page
Table
Table 14, "LVIO DC Electrical Characteristics," on page
Table 15, "UHVIO DC Electrical Characteristics," on page
Table 115. i.MX53xA Data Sheet Document Revision History
20.
Figure 27, "DTACK Write Access (DAP=0)," on page
Table 18, "DDR Output Driver Average Impedance," on page
11,
156.
Table 64, "Asynchronous Parallel Interface Timing Parameters (Access Level)," on page
Table 1, "Ordering Information," on page
Figure 2, "Power Up Detailed Sequence," on page
Table 35, " NFC—Timing Characteristics," on page
Table 63, "Asynchronous Display Interface Timing Parameters (Pixel Level)," on page
Table 102, "USB Timing Specification for Normal ULPI Mode," on page
.
Table
Figure 18
12, and
Section 4.4.2, “DDR Output Driver Average
page 6
through
Table 10
Table
in
Section 4.7.8.6.1, “IPU Display Operating Signals.”
Section 1.2,
Table 32, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page
DDR3). Changes include adding LPDDR2 waves, updating timings by
13, changed input current from the nA range to 1 μA.
Figure
Table 113, "19 x 19 mm Signal Assignments, Power Rails, and I/O,"
through
Substantive Change(s)
”
row from
26, to fit original EIM AC spec.
“Features.”
Table
updated the caution note on
Table 29, "AC Electrical Characteristics of LVDS Pad,"
Table 8, "Maximal Supply Currents," on page
15.
3.
Section 4.6.7, “DDR SDRAM Specific Parameters
Table 6, "i.MX53xA Operating Ranges," on
32, changed input current with no
24, removed the row for Suspend
26.
61.
33, changed input current with no
51.
28, changed input current with no
Impedance,” from “LPDDR2 I/O
37.
page
18.
146.
Revision History
22.
104.
105.
46.
175