PCA9575PW2,118 NXP Semiconductors, PCA9575PW2,118 Datasheet
PCA9575PW2,118
Specifications of PCA9575PW2,118
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PCA9575PW2,118 Summary of contents
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PCA9575 16-bit I with reset and interrupt Rev. 03 — 9 November 2009 1. General description The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery ...
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... NXP Semiconductors Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os as inputs, sets the registers to their default values and initializes the device state machine. The I/O banks are held in its default state when the logic supply (V The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages, and is specifi ...
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... NXP Semiconductors 3. Applications I Cell phones I Media players I Multi-voltage environments I Battery operated mobile gadgets I Motherboards I Servers I RAID systems I Industrial control I Medical equipment I PLCs I Gaming machines I Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9575PW2 PCA9575PW2 PCA9575PW1 PA9575PW1 ...
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... NXP Semiconductors 5. Block diagram SCL SDA V DD RESET V SS (1) PCA9575PW2 only. Fig 1. PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO PCA9575 2 I C-BUS/SMBus INPUT FILTER POWER-ON RESET Remark: All I/Os are set to inputs at power-up and RESET. ...
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... NXP Semiconductors data from shift register configuration register data from D Q shift register FF write configuration CK Q pulse write pulse read pulse BUS-HOLD AND PULL-UP/PULL-DOWN CONTROL data from shift register write polarity pulse Fig 2. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7) ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning RESET P0_0 3 P0_1 4 5 P0_2 6 P0_3 PCA9575PW1 V 7 DD(IO)0 P0_4 8 9 P0_5 P0_6 10 P0_7 11 INT 12 Fig 3. Pin configuration for TSSOP24 Fig 5. Pin configuration for HWQFN24 PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol RESET P0_0 P0_1 P0_2 P0_3 A1 V DD(IO)0 P0_4 P0_5 P0_6 P0_7 INT P1_7 P1_6 P1_5 P1_4 V DD(IO)1 A3 P1_3 P1_2 P1_1 P1_0 SDA SCL [1] HWQFN24 package die supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board ...
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... NXP Semiconductors 7. Functional description 7.1 I/O ports The 16 I/O ports are organized as two banks of 8 ports each. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register ...
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... NXP Semiconductors 7.3 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9575, which will be stored in the Command register. Fig 8. The lowest 4 bits are used as a pointer to determine which register will be accessed. Only a Command register code with the 4 least signifi ...
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... NXP Semiconductors Table 3. Register summary …continued Register number D3 D2 0Dh 1 1 0Eh 1 1 0Fh 1 1 7.5 Writing to port registers Data is transmitted to the PCA9575 by sending the device address and setting the least significant bit to logic 0 (see is sent after the address and determines which register will receive the data following the command byte ...
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... NXP Semiconductors 7.6.2 Register 1 - Input port 1 register This register is read-only. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register will be acknowledged but will have no effect. ...
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... NXP Semiconductors 7.6.4 Register 3 - Polarity inversion port 1 register This register allows the user to invert the polarity of the Input port register data bit in this register is set (written with ‘1’), the corresponding Input port data is inverted bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. ...
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... NXP Semiconductors 7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the pull-up/pull-downs will be disabled for I/O bank 1. Setting the bit 0 to logic 0 disables bus-hold feature ...
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... NXP Semiconductors 7.6.7 Register 6 - Pull-up/pull-down select port 0 register When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O port 0 can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for that I/O pin ...
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... NXP Semiconductors 7.6.9 Register 8 - Configuration port 0 register This register configures the direction of the I/O pins bit in this register is set (written with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance output driver bit in this register is cleared (written with logic 0), the corresponding port 0 pin is enabled as an output. At reset, the device’ ...
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... NXP Semiconductors 7.6.11 Register 10 - Output port 0 register This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 8. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value ...
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... NXP Semiconductors 7.6.13 Register 12 - Interrupt mask port 0 register All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to logic 0. Table 16. Legend: * default value. Bit 7.6.14 Register 13 - Interrupt mask port 1 register All the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software reset, thus disabling interrupts ...
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... NXP Semiconductors 7.6.15 Register 14 - Interrupt status port 0 register This register is read-only used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros. Table 18. Legend: * default value. Bit 7.6.16 Register 15 - Interrupt status port 1 register This register is read-only used to identify the source of interrupt. ...
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... NXP Semiconductors 7.9 Software reset The Software Reset Call allows all the devices in the I state value through a specific formatted I implies that the I The Software Reset sequence is defined as following START command is sent by the I 2. The reserved General Call I is sent by the I 3. The PCA9575 device(s) acknowledge(s) after seeing the General Call address ‘ ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 11. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see and Figure Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 16). SCL (1) slave address SDA START condition write to port data out from port (1) Slave address shown in this example is for the 24-pin version ...
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... NXP Semiconductors (1) slave address SDA START condition acknowledge from slave (1) slave address (cont (repeated) START condition (1) Slave address shown in this example is for the 24-pin version. Fig 15. Read from register data into port INT t v(INT) SCL slave address SDA START condition read from port This fi ...
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... NXP Semiconductors 10. Application design-in information 3.6 V 1 MASTER CONTROLLER SCL SDA INT RESET V SS Address pin connections shown are for the 28-pin version. Device address configured as 0100 101Xb for this example. P0_0, P0_2, P0_3 configured as outputs; P0_1, P0_4 to P0_7 and P1_0 to P1_7 configured as inputs. ...
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... NXP Semiconductors 12. Static characteristics Table 21. Static characteristics DD(IO)0 otherwise specified. Symbol Parameter Supplies V supply voltage DD V input/output supply voltage 0 DD(IO)0 V input/output supply voltage 1 DD(IO)1 I supply current DD I LOW-level standby current stbL I HIGH-level standby current stbH V power-on reset voltage POR Input SCL ...
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... NXP Semiconductors Table 21. Static characteristics DD(IO)0 otherwise specified. Symbol Parameter Interrupt INT I LOW-level output current OL Select inputs (reset and address) V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current LI C input capacitance i 3 (V) 2.0 1 Fig 18 3 DD(IO)n ...
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... NXP Semiconductors (mA amb + 0.2 0 1.8 V DD(IO)0 DD(IO)1 Fig 21. I versus 13. Dynamic characteristics Table 22. Dynamic characteristics DD(IO)0 otherwise specified. Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START HD ...
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... NXP Semiconductors Table 22. Dynamic characteristics DD(IO)0 otherwise specified. Symbol Parameter Port timing t data output valid time v(Q) t data input set-up time su(D) t data input hold time h(D) Interrupt timing t valid time on pin INT v(INT) t reset time on pin INT ...
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... NXP Semiconductors SCL SDA RESET rec(rst) P0_0 to P0_7 P1_0 to P1_7 Fig 23. Reset timing 14. Test information R = load resistance load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T (1) For SDA, no 500 pull-down. Fig 24. Test circuitry for switching times ...
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... NXP Semiconductors 15. Package outline TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 0.75 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0.30 mm 0.8 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 25. Acronym CBT CDM CMOS DUT ESD GPIO HBM I C-bus IC LED LP MM PLC ...
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... NXP Semiconductors 19. Revision history Table 26. Revision history Document ID Release date PCA9575_3 20091109 • Modifications: Added Figure 20 “I • Added Figure 21 “I PCA9575_2 20090727 PCA9575_1 20081002 PCA9575_3 Product data sheet 2 16-bit I C-bus and SMBus, level translating, low voltage GPIO Data sheet status ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . . 8 7.1 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.2 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 Command register . . . . . . . . . . . . . . . . . . . . . . 9 7.4 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.5 Writing to port registers . . . . . . . . . . . . . . . . . 10 7 ...