X96010V14I Intersil, X96010V14I Datasheet - Page 13

• Manufacturer Part Number: X96010V14I
• Description: CONDITIONER SGNL DUAL MEM & DAC
• Manufacturer: Intersil
• Type: Sensor Conditionerr

Specifications of X96010V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

L2DAS: LUT2 D
VOLATILE
When bit L2DAS is set to “0” (default), LUT2 is
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “1”, LUT2 is addressed by
bits L2DA5 - L2DA0.
D2DAS: D/A 2 D
VOLATILE
When bit D2DAS is set to “0” (default), the input to the
D/A converter 2 is a row of LUT2. When bit D2DAS is set
to “1”, that input is the content of the Control register 4.
Control Register 6
This register is accessed by performing a Read or
Write operation to address 86h of memory.
WEL: W
The WEL bit controls the Write Enable status of the
entire X96010 device. This bit must be set to “1” before
any other Write operation (volatile or nonvolatile). Oth-
erwise, any proceeding Write operation to memory is
aborted and no ACK is issued after a Data Byte.
RITE
)
)
E
NABLE
IRECT
IRECT
L
A
A
ATCH
CCESS
CCESS
13
(V
S
OLATILE
S
ELECT
ELECT
B
)
B
IT
IT
(N
(N
ON
ON
-
-
X96010
The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
10000000
WEL bit remains set to “1” until the X96010 is powered
down, and then up again, or until it is reset to “0” by
writing 00000000
A Write operation that modifies the value of the WEL bit
will not cause a change in other bits of Control register 6.
Status Register - ADC Output
This register is accessed by performing a Read opera-
tion to address 87h of memory.
AD7 - AD0: A/D C
ONLY
These eight bits are the binary output of the on-chip
A/D converter. The output is 00000000
input and 11111111
MSBs select a row of the LUTs.
)
2
to Control register 6. Once enabled, the
2
ONVERTER
to Control register 6.
2
for full scale input. The six
O
UTPUT
B
2
ITS
for minimum
October 25, 2005
(R
EAD
FN8214.1