DS1876T+T&R Maxim Integrated Products, DS1876T+T&R Datasheet - Page 18

• Manufacturer Part Number: DS1876T+T&R
• Description: IC CTRLR SFP DUAL LDD 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP Laser Controllerr

Specifications of DS1876T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SFP Controller with Dual LDD Interface
Figure 9. Logic Diagram 1
Figure 10. Logic Diagram 2
Six digital input pins and five digital output pins are pro-
vided for monitoring and control.
Digital input pins IN1 and RSEL primarily serve to meet
the rate-select requirements of SFP and SFP+. They
can also serve as general-purpose inputs. OUT1 and
RSELOUT are driven by a combination of the IN1, RSEL,
and logic dictated by control registers in the EEPROM
(see Figure 10). The levels of IN1 and RSEL can be
read from the STATUS register (Lower Memory, Register
6Eh). The open-drain output OUT1 can be controlled
and/or inverted using the CNFGB register (Table 02h,
18
TXP HI ENABLE
TXP_ HI FLAG
HBAL ENABLE
HBAL_ FLAG
TXP_ LO FLAG
RSEL
_____________________________________________________________________________________
QTHEXT_
TXDC_
IN1
TXP LO ENABLE
TXD_
R
PU
TXD
V
CC
EXT
RSELC
IN1S
IN1C
RSELS
(t
INITR1
)
INVRSOUT
TXDS_
INVOUT1
IN1, RSEL, OUT1, RSELOUT
FAULT RESET TIMER
OUT
OUT
IN
(130ms)
= PINS
Digital I/O Pins
IN
C
C
D
R
S
Q
Q
OUT1
RSELOUT
POWER-ON
RESET
Register 89h). The open-drain RSELOUT output is
software controlled and/or inverted through the STATUS
register and CNFGA register (Table 02h, Register 88h).
External pullup resistors must be provided on OUT1 and
RSELOUT to realize high logic levels.
TXDOUT1 and TXDOUT2 are generated from a com-
bination of TXF1, TXF2, TXD1, TXD2, and the internal
signals FETG1 and FETG2 (Table 02h, Register 8Ah). A
software control identical to TXD1 and TXD2 is also avail-
able (TXDC1 and TXDC2, Lower Memory, Register 6Eh).
A TXD1 or TXD2 pulse is internally extended (TXD
by time t
warnings related to the APC loop to allow for the loop to
stabilize. The nonlatching alarms and warnings are TXP
LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2
LO. In addition, TXP LO is disabled from creating FETG.
See the Transmit Fault (TXFOUT) Output section for a
detailed explanation of TXFOUT. As shown in Figure 9,
the same signals and faults can also be used to gener-
ate the internal signal FETG. FETG is used to send a fast
“turn-off” command to the laser driver. The intended use
is a direct connection to the laser driver’s TXD1, TXD2
input if this is desired. When V
TXDOUT2 are high impedance.
SET BIAS_ DAC AND
MOD_ DAC TO HIGH
IMPEDANCE
FETG_
NOTE:
_ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2.
INITR1
REFERS TO A PIN.
INVTXF_
TXFINT
TXF_
TXDFLT_
to inhibit the latching of low alarms and
TXDFG_
TXDIO_
TXD_
TXF1, TXF2, TXFOUT, TXD1, TXD2,
TXFS_
CC
TXFOUTS1
TXFOUTS2
< POA, TXDOUT1 and
TXDOUT1, TXDOUT2
TXFOUTS_
TXDOUT_
TXFOUT
EXT
)