DS1876T+T&R Maxim Integrated Products, DS1876T+T&R Datasheet - Page 21

• Manufacturer Part Number: DS1876T+T&R
• Description: IC CTRLR SFP DUAL LDD 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP Laser Controllerr

Specifications of DS1876T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 10mA
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

See Figure 13 for an example of I
Figure 13. Example I
A)
B)
C)
D)
TYPICAL I
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
EXAMPLE I
START
always the second byte transmitted during a write
operation following the slave address byte.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember that the master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes
the memory address, writes up to 8 data bytes, and
generates a STOP condition. The DS1876 writes 1 to
8 bytes (one page or row) with a single write trans-
action. This is internally controlled by an address
counter that allows data to be written to consecutive
addresses without transmitting a memory address
before each data byte is sent. The address counter
limits the write to one 8-byte page (one row of the
memory map). Attempts to write to additional pages
of memory without sending a STOP condition between
pages result in the address counter wrapping around
to the beginning of the present row.
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h TO
REGISTERS C8h AND C9h
TWO-BYTE READ
-READ C8h AND C9h
2
C WRITE TRANSACTION
2
MSB
C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS
X
X
X
ADDRESS*
______________________________________________________________________________________
SLAVE
2
X
C Timing
SFP Controller with Dual LDD Interface
START
START
START
START
0
0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1
A2h
A2h
A2h
A2h
WRITE
READ/
LSB
R/W
2
C timing.
SLAVE
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
ACK
I
2
MSB
1 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0
1 1 0 0 1 0 0 0
1 1 0 0 1 0 0 0
b7
C Protocol
BAh
BAh
C8h
C8h
b6
b5
REGISTER ADDRESS
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
b4
b3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
REPEATED
REPEATED
START
START
b2
00h
01h
b1
For example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h would contain 11h and 22h, respec-
tively, and the third data byte, 33h, would be written
to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM write
time to elapse. Then the master can generate a new
START condition and write the slave address byte
(R/W = 0) and the first memory address of the next
memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM page is
written, the DS1876 requires the EEPROM write time
(t
the page to EEPROM. During the EEPROM write time,
the DS1876 does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
DS1876, which allows the next page to be written
as soon as the DS1876 is ready to receive the data.
The alternative to acknowledge polling is to wait for
maximum period of t
to write again to the DS1876.
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
WR
LSB
SLAVE
SLAVE
b0
ACK
ACK
A3h
A3h
) after the STOP condition to write the contents of
SLAVE
ACK
0 1 1 1 0 1 0 1
STOP
75h
SLAVE
SLAVE
MSB
ACK
ACK
b7
b6
DATA IN BAh
DATA IN C8h
SLAVE
ACK
DATA
DATA
b5
WR
STOP
b4
DATA
to elapse before attempting
MASTER
MASTER
b3
NACK
ACK
b2
STOP
DATA IN C9h
b1
DATA
LSB
b0
SLAVE
ACK
MASTER
NACK
STOP
STOP
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