DS32ELX0421SQX/NOPB National Semiconductor, DS32ELX0421SQX/NOPB Datasheet - Page 12

• Manufacturer Part Number: DS32ELX0421SQX/NOPB
• Description: IC SERIALIZER 312.5GBPS 48LLP
• Manufacturer: National Semiconductor

Specifications of DS32ELX0421SQX/NOPB

• Function: Serializer
• Data Rate: 3.125Gbps
• Input Type: LVDS
• Output Type: CML
• Number Of Inputs: 5
• Number Of Outputs: 2
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS32ELX0421SQX

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Functional Description
POWER SUPPLIES
The DS32EL0421 and DS32ELX0421 have several power
supply pins, at 2.5V as well as 3.3V. It is important that these
pins all be connected and properly bypassed. Bypassing
should consist of parallel 4.7μF and 0.1μF capacitors as a
minimum, with a 0.1μF capacitor on each power pin. A 22 μF
capacitor is required on the VDDPLL pin which is connected
to the 3.3V rail.
These devices have a large contact in the center on the bot-
tom of the package. This contact must be connected to the
system GND as it is the major ground connection for the de-
vice.
POWER UP
It is recommended, although not necessary, to bring up the
3.3V power supply before the 2.5V supply. If the 2.5V supply
is powered up first, an initial current draw of approximately
600mA from the 2.5V rail may occur before settling to its final
value. Regardless of the sequence, both power rails should
monotonically ramp up to their final values.
POWER MANAGEMENT
These devices have two methods to reduce power consump-
tion. To enter the first power save mode, the on board host
FPGA or controlling device can cease to output the DDR
transmit clock. To further reduce power consumption, write
40'h to register 26'h and 10'h to register 01'h. This will put the
device in its lowest power consumption mode.
RESET
There are three ways to reset these devices. A reset occurs
automatically during power-up. The device can also be reset
by pulling the RESET pin low, with normal operation resuming
when the pin is driven high again. The device can also be
reset by writing to the reset register. This reset will put all of
the register values back to their default values, except it will
not affect the address register value if the SMBus default ad-
dress has been changed.
LVDS INPUTS
The DS32EL0421 and DS32ELX0421 have standard 2.5V
LVDS inputs which are compliant with ANSI/TIA/EIA-644.
These inputs have internal 100Ω termination resistors. It is
recommended that the PCB trace between the FPGA and the
serializer be less than 40-inches. Longer PCB traces may
degrade the quality of the input signal. The connection be-
tween the host and the DS32EL0421 or DS32ELX0421
should be over a controlled impedance transmission line with
impedance that matches the termination resistor – usually
100Ω. Setup and hold times are specified in the LVDS Switch-
ing Characteristics table, however the clock delay can be
adjusted by writing to register 30’h.
LOOP FILTER
The DS32EL0421 and DS32ELX0421 have an internal PLL
which is used to generate the serialization clock from the par-
allel clock input. The loop filter for this PLL is external; and for
optimum results, a 100nF capacitor and a 1.5 kΩ resistor in
series should be connected between pins 26 and 27. See
typical interface circuit
CML LAUNCH AMPLITUDE
The launch amplitude of the CML output(s) is controlled by
placing a single resistor from the VOD_CTRL pin to ground.
(Figure
12).
12
Use the following equation to obtain the desired V
lecting the corresponding resistor value.
The CML output launch amplitude can also be adjusted by
writing to SMBus register 69'h, bits 2:0. This register is meant
to assist system designers during the initial prototype design
phase. For final production, it is recommended that the ap-
propriate resistor value be selected for the desired V
that register 69'h be left to its default value.
REMOTE SENSE
The remote sense feature can be used when a DS32EL0421
or DS32ELX0421 serializer is directly connected to a
DS32EL0124 or DS32ELX0124 deserializer. Active compo-
nents in the signal path between the serializer and the dese-
rializer may interfere with the back channel signaling of the
devices.
When remote sense is enabled, the serializer will cycle
through four states to successfully establish a link and align
the data. The state diagram for the serializer is shown in
ure
until it receives an input clock. Once the PLL of the serializer
has locked to the input clock, the device will enter the LINK
DETECT state. While in this state, the serializer will monitor
the line to see if the deserializer is present. If a deserializer is
detected, the serializer will enter the LINK ACQUISITION
state. The serializer will transmit the entire training pattern
and then enter the NORMAL state. If the deserializer is unable
to successfully lock or maintain lock it will break the link,
sending the serializer back to the IDLE or LINK DETECT
states.
With the Remote Sense feature active, the serializer can be
forced out of lock due to events on the high speed serial line
in two ways, a serial channel reset signal is sent upstream
from the deserializer or the near end termination detect circuit
signals and open termination was detected. The upstream
signal sent from the deserializer that resets the serializer is
called the link detect signal. Since the serializer and deseri-
alizer may power up at different times, the deserializer will
transmit this link detect signal periodically, once it detects that
a serializer is active on the other side of the high speed line.
When a serializer receives the link detect signal, it will return
to the LINK DETECT state. The near end open termination
detection circuit will trigger only for near end open termination
events, such as unplugging the cable on the serializer end of
the line.
DC-BALANCE ENCODER
The DS32EL0421 and DS32ELX0421 have a built-in DC-bal-
ance encoder to support AC-coupled applications. When en-
abled, the input signal on TXIN4+/- is treated as a data valid
bit. If TXIN4+/- is low, then the four bit nibbles from TXIN0-
TXIN3 are taken to form a 16 bit word. This 16 bit word is
processed as two 8 bit words and converted to two 10 bit
words by using the standard 8b/10b data coding scheme. The
two 10 bit words are then combined to create a 20 bit code.
This 20 bit word is serialized and driven on the output. The
nibble taken in on the rising edge of the clock is the most sig-
nificant nibble and the nibble taken in on the falling edge is
the least significant nibble. If TXIN4+/TXIN4- is high, then the
inputs TXIN0 -TXIN3 are ignored and a programmable DC-
balanced SYNC character is inserted in the output stream.
The default character is a K28.5 code. In order to send other
K codes, they must first be programmed into the serializer via
the SMBus. The SMBus registers allows for only a single pro-
grammable character.
7. The serializer will remain in the low power IDLE state
R = (1400 mV / V
OD
) x 9.1 kΩ
OD
OD
by se-
Fig-
and