DS32ELX0421SQX/NOPB National Semiconductor, DS32ELX0421SQX/NOPB Datasheet - Page 15

• Manufacturer Part Number: DS32ELX0421SQX/NOPB
• Description: IC SERIALIZER 312.5GBPS 48LLP
• Manufacturer: National Semiconductor

Specifications of DS32ELX0421SQX/NOPB

• Function: Serializer
• Data Rate: 3.125Gbps
• Input Type: LVDS
• Output Type: CML
• Number Of Inputs: 5
• Number Of Outputs: 2
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS32ELX0421SQX

SMBus INTERFACE
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. The use of the Chip
Select signal is required. Holding the SMB_CS pin HIGH en-
ables the SMBus port, allowing access to the configuration
registers. Holding the SMB_CS pin LOW disables the
device's SMBus, allowing communication from the host to
other slave devices on the bus. In the STANDBY state, the
System Management Bus remains active. When communi-
cation to other devices on the SMBus is active, the SMB_CS
signal for the serializer must be driven LOW.
The address byte for all DS32EL0421 and DS32ELX0421
devices is AE'h. Based on the SMBus 2.0 specification, these
devices have a 7-bit slave address of 1010111'b. The LSB is
set to 0'b (for a WRITE), thus the 8-bit value is 1010 1110 'b
or AE'h.
The SCK and SDA pins are 3.3V LVCMOS signaling and in-
clude high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon
SMBus loading and speed. Note, these pins are not 5V tol-
erant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCK is HIGH.
There are three unique states for the SMBus:
SMBus Transactions
The devices support WRITE and READ transactions. See
Register Description Table for register address, type (Read/
Write, Read Only), default value and function information.
Writing to a Register
To write a register, the following protocol is used (see SMBus
2.0 specification).
1.
2.
3.
4.
5.
6.
7.
8.
START A HIGH to LOW transition on SDA while SCK is
STOP
IDLE
The Host (Master) selects the device by driving its
SMBus Chip Select (SMB_CS) signal HIGH.
The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drive the 8-bit data byte.
The Device drives an ACK bit (“0”).
The Host drives a STOP condition.
HIGH indicates a message START condition
A LOW to HIGH transition on SDA while SCK is
HIGH indicates a message STOP condition.
If SCK and SDA are both high for a time exceeding
t
are HIGH for a total exceeding the maximum
specification for t
the IDLE state.
BUF
from the last detected STOP condition or if they
HIGH
then the bus will transfer to
15
9.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus
2.0 specification).
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. The Host drives a NACK bit “1”indicating end of the
11. The Host drives a STOP condition.
12. The Host de-selects the device by driving its SMBus CS
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
SMBus Configurations
Many different configurations of the SMBus are possible and
depend upon the specific requirements of the applications.
Several possible applications are described.
Configuration 1
The deserializer SMB_CS may be tied High (always enabled)
since it is the only device on the SMBus. See
Configuration 2
Since the multiple SER devices have the same address, the
use of the individual SMB_CS signals is required. To com-
municate with a specific device, its SMB_CS is driven High to
select the device. After the transaction is complete, its
SMB_CS is driven Low to disable its SMB interface. Other
devices on the bus may now be selected with their respective
chip select signals and communicated with. See
Configuration 3
The addressing field is limited to 7-bits by the SMBus protocol.
Thus it is possible that multiple devices may share the same
7-bit address. An optional feature in the SMBus 2.0 specifi-
cation supports an Address Resolution Protocol (ARP). This
optional feature is not supported by the DS32EL0421/
DS32ELX0421 devices. Solutions for this include: the use of
the independent SMB_CS signals, independent SMBus seg-
ments, or other means.
The Host de-selects the device by driving its SMBus CS
signal Low.
The Host (Master) selects the device by driving its
SMBus Chip Select (SMB_CS) signal HIGH.
The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drives a START condition.
The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
The Device drives an ACK bit “0”.
The Device drives the 8-bit data value (register contents).
READ transfer.
signal Low.
Figure
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Figure
8.
9.