PCA9515DP,118 NXP Semiconductors, PCA9515DP,118 Datasheet

IC I2C BUS REPEATER 8-TSSOP

PCA9515DP,118

Manufacturer Part Number
PCA9515DP,118
Description
IC I2C BUS REPEATER 8-TSSOP
Manufacturer
NXP Semiconductors
Type
Repeaterr
Datasheet

Specifications of PCA9515DP,118

Package / Case
8-TSSOP
Tx/rx Type
I²C Logic
Delay Time
55ns
Capacitance - Input
6pF
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
2.3mA
Mounting Type
Surface Mount
Logic Family
PCA9515
Operating Supply Voltage
2.3 V to 3.6 V
Power Dissipation
100 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5.5 V
Logic Type
I2C Bus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Output Current
50 mA
Output Voltage
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1034-2
935268635118
PCA9515DP-T
1. General description
2. Features
The PCA9515 is a BiCMOS integrated circuit intended for application in I
SMBus systems.
While retaining all the operating modes and features of the I
extension of the I
thus enabling two buses of 400 pF.
The I
Using the PCA9515 enables the system designer to isolate two halves of a bus, thus more
devices or longer length can be accommodated. It can also be used to run two buses, one
at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is
isolated when 400 kHz operation of the other is required.
Two or more PCA9515s cannot be put in series. The PCA9515 design does not allow
this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage levels
are used to avoid lock-up conditions between the input and the output. A ‘regular low’
applied at the input of a PCA9515 will be propagated as a ‘buffered low’ with a slightly
higher value. When this ‘buffered low’ is applied to another PCA9515, PCA9516A, or
PCA9518A in series, the second PCA9515, PCA9516A, or PCA9518A will not recognize
it as a ‘regular low’ and will not propagate it as a ‘buffered low’ again. The
PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the
PCA9515, PCA9516A, or PCA9518A but can be used in series with themselves since
they use shifting instead of static offsets to avoid lock-up conditions.
The PCA9515 SCLn/SDAn C
The newer PCA9515A should be used in applications where power is secured to the
repeater but an active bus remains on either set of SCLn/SDAn pins to prevent this
increase in bus loading. Additionally, the PCA9515A has a wider voltage range of 2.3 V to
3.6 V and can be used in applications with lower voltage supply constraints.
I
I
I
I
I
I
I
I
I
PCA9515
I
Rev. 09 — 23 April 2009
2 channel, bidirectional buffer
I
Active HIGH repeater enable input
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates Standard-mode and Fast-mode I
Powered-off high-impedance I
Operating supply voltage range of 3.0 V to 3.6 V
2
2
C-bus and SMBus compatible
2
C-bus repeater
C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
2
C-bus by buffering both the data (SDAn) and the clock (SCLn) lines,
i
is about 200 pF versus the normal < 10 pF when V
2
C-bus pins
2
C-bus devices and multiple masters
2
C-bus system, it permits
Product data sheet
2
C-bus and
CC
= 0 V.

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PCA9515DP,118 Summary of contents

Page 1

PCA9515 2 I C-bus repeater Rev. 09 — 23 April 2009 1. General description The PCA9515 is a BiCMOS integrated circuit intended for application in I SMBus systems. While retaining all the operating modes and features of the I extension ...

Page 2

... NXP Semiconductors I 5.5 V tolerant 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8 and TSSOP8 (MSOP8) 3. Ordering information Table 1 ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 3. Symbol n.c. SCL0 SDA0 GND EN SDA1 SCL1 V CC PCA9515_9 Product data sheet SCL0 SCL1 PCA9515D SDA0 3 6 SDA1 GND 002aac743 Pin configuration for SO8 Pin description Pin Description ...

Page 4

... NXP Semiconductors 6. Functional description The PCA9515 BiCMOS integrated circuit contains two identical buffer circuits which enable I performance. (Refer to The PCA9515 BiCMOS integrated circuit contains two bidirectional open-drain buffers specifically designed to support the standard low-level-contention arbitration of the 2 I C-bus. Except during arbitration or clock stretching, the PCA9515 acts like a pair of non-inverting, open-drain buffers, one for SDA and one for SCL ...

Page 5

... NXP Semiconductors 7. Application design-in information A typical application is shown 3 unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. Fig 4. The PCA9515 tolerant so it does not require any additional circuitry to translate between the different bus voltages. ...

Page 6

... NXP Semiconductors SCL SDA V of master OL Fig 5. Bus 0 waveform SCL SDA Fig 6. Bus 1 waveform 8. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to GND. Symbol bus I P tot T stg T amb PCA9515_9 Product data sheet ...

Page 7

... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics 3.6 V; GND = Symbol Parameter Supplies V supply voltage CC I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply current CCLc Input SCLn; input/output SDAn V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage ...

Page 8

... NXP Semiconductors 10. Dynamic characteristics Table 6. Dynamic characteristics 3.6 V; GND = Symbol Parameter t HIGH to LOW propagation delay PHL t LOW to HIGH propagation delay PLH t HIGH to LOW output transition time THL t LOW to HIGH output transition time TLH t set-up time su t hold time h [1] The t transition time is specifi ...

Page 9

... NXP Semiconductors 12. Package outline SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 11

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 12

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 13

... NXP Semiconductors Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 9. Acronym BiCMOS CDM DUT ESD HBM 2 I C-bus MM RC SMBus PCA9515_9 Product data sheet ...

Page 14

... Release date PCA9515_9 20090423 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 1 “General – 4 – Added new 5 • ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Enable 6.2 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application design-in information . . . . . . . . . . 5 8 Limiting values Static characteristics Dynamic characteristics ...

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