PCA9558PW,112 NXP Semiconductors, PCA9558PW,112 Datasheet
PCA9558PW,112
Specifications of PCA9558PW,112
935269433112
PCA9558PW
Related parts for PCA9558PW,112
PCA9558PW,112 Summary of contents
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PCA9558 8-bit I latched 6-bit I Rev. 04 — 14 April 2009 1. General description The PCA9558 is a highly integrated, multi-function device that is composed of a 5-bit multiplexed/1-bit latched 6-bit I and a 2-kbit serial EEPROM with write ...
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... NXP Semiconductors I 2 tolerant inputs I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 3. Applications I Board version tracking and configuration I Board health monitoring and status reporting ...
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... NXP Semiconductors 5. Block diagram PCA9558 MUX_SELECT MUX_OUT_LOW MUX_INA to MUX_INE A0 SCL INPUT FILTER SDA POWER- RESET IO_OUT_LOW Fig 1. Block diagram of PCA9558 PCA9558_4 Product data sheet 6-bit EEPROM C-BUS INTERFACE LOGIC C-BUS CONTROL LOGIC 256-BYTE EEPROM Rev. 04 — 14 April 2009 PCA9558 2 8-bit I C-bus/SMBus I/O port ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol SCL SDA IO_OUT_LOW A0 MUX_INA MUX_INB MUX_INC MUX_IND MUX_INE V SS IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 PCA9558_4 Product data sheet SCL 1 2 SDA 3 IO_OUT_LOW A0 4 MUX_INA 5 6 MUX_INB ...
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... NXP Semiconductors Table 2. Symbol MUX_SELECT MUX_OUTE MUX_OUTD MUX_OUTC MUX_OUTB MUX_OUTA NON_MUXED_OUT MUX_OUT_LOW Functional description Refer to 2 7.1 I C-bus interface Communicating with this device is initiated by sending a valid address on the I address format (see a 1-bit read/write value which determines the direction of the data transfer. ...
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... NXP Semiconductors Table 7.1.1 Multiplexer Fig 5. Fig 6. PCA9558_4 Product data sheet Command byte MSB NON- MUX 0 0 MUXED DATA E DATA 2 I C-bus MUX_OUTx data byte MSB MUX_IN C-bus MUX_INx data byte Rev. 04 — 14 April 2009 PCA9558 2 8-bit I C-bus/SMBus I/O port D0 Command ...
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... NXP Semiconductors The Multiplexer function controls the six open-drain outputs, MUX_OUTx and NON_MUXED_OUT. This control is affected by the input pins MUX_SELECT (pin 19), MUX_OUT_LOW (pin 26), and/or an internal register programmed via the I Upon power-up, the multiplex function is controlled by the MUX_SELECT and MUX_OUT_LOW pins. When the MUX_SELECT signal is a logic 0, the multiplexer will select the data from the 6-bit EEPROM to drive on the MUX_OUTx and NON_MUXED_OUT pins ...
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... NXP Semiconductors slave address START condition 2 Fig 7. I C-bus write for MUXCNTRL register slave address START condition 2 Fig 8. I C-bus read for MUXCNTRL register 7.1.2 Registers The GPIOs are controlled by a set of 4 internal registers: Input Port (IP) register; Output Port (OP) register; Polarity Inversion (PI) register; and the Input/Output Configuration (IOC) register ...
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... NXP Semiconductors 7.1.2 Output Port register This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined as outputs in the IOC register. Bit values in this register have no effect on GPIO defined as inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling the output, not the actual output value ...
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... NXP Semiconductors slave address START condition See Table 3 for the proper command byte. 2 Fig 9. I C-bus write for GPIO registers slave address START condition 2 Fig 10. I C-bus read for GPIO registers slave address START condition 2 Fig 11. I C-bus read of MUX_INx inputs ...
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... NXP Semiconductors 7.1.3 EEPROM write operation 7.1.3.1 6-bit write operation A write operation to the 6-bit EEPROM requires that an address byte be written after the command byte. This address points to the 6-bit address space in the EEPROM array. Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the EEPROM ...
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... NXP Semiconductors 7.1.3.3 256-byte write operation (I A write operation to the 256-byte EEPROM requires that an address byte be written after the command byte. This address points to the starting address in the EEPROM array. The four LSBs of this address select a position on a 16-byte page register, the 4 MSBs select which page register. The four LSBs will be auto-incremented after receipt of each byte of data ...
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... NXP Semiconductors slave address START condition slave address (cont (re)START condition M bytes where Fig 15. I C-bus read operation from 256-byte EEPROM 7.1.3.5 256-byte EEPROM write to GPIO A mode is available whereby a byte of data in the 256-byte EEPROM array can be written to the GPIO (OP register). This is initiated by the I indicating a read from the 256-byte EEPROM and write to the GPIO is sent, followed by the word address of the data within the EEPROM array ...
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... NXP Semiconductors When the Write Protect (WP) input is a logic 0 it allows writes to both EEPROM arrays. When logic 1, it prevents any writes to the EEPROM arrays. slave address START condition R/W See Table 3 for the needed command code. Fig 17. Read from GPIO Input Port register and write to 256-byte EEPROM 7 ...
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... NXP Semiconductors (EEPROM address), and then the Data1 (data byte). A read from the EEPROM would be a two-step process. The first step would ‘Write Byte’ with the EEPROM address in the Data0 register. The second step would ‘Receive Byte’ where the data is stored in the command register. Other differences from the SMBus specifi ...
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... NXP Semiconductors 9. Limiting values Table 9. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V Symbol stg [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C ...
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... NXP Semiconductors 11. Static characteristics Table 11. Static characteristics Symbol Parameter Supply V supply voltage DD I LOW-level supply current CCL I HIGH-level supply current CCH V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I HIGH-level leakage current ...
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... NXP Semiconductors 12. Dynamic characteristics Table 12. Dynamic characteristics Symbol Parameter MUX_INx to MUX_OUTx t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL MUX_SELECT to MUX_OUTx t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay PHL MUX_OUT_LOW to NON_MUXED_OUT t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 19. Definition of timing Fig 20. Open-drain output enable and disable times 13. Non-volatile storage specifications Table 13. Parameter memory cell data retention number of memory cell write cycles PCA9558_4 Product data sheet HD;DAT HIGH SU;DAT ...
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... NXP Semiconductors 14. Test information Fig 21. Test circuit for open-drain outputs PCA9558_4 Product data sheet PULSE GENERATOR R = load resistor ( load capacitance (includes jig and probe capacitance termination resistance; should be equal Rev. 04 — 14 April 2009 PCA9558 2 8-bit I C-bus/SMBus I/O port DUT 002aac532 ...
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... NXP Semiconductors 15. Package outline TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 16. Acronym ASIC CDM CPU DIP DUT EEPROM ESD GPIO HBM I C-bus LED ...
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... PCA9558_4 20090414 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Pin name “GND” changed to “V • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 2 7.1 I C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 Multiplexer 7.1.2 Registers 7.1.2 Input Port register 7.1.2 Output Port register . . . . . . . . . . . . . . . . . 9 7 ...