PCA9703PW,118 NXP Semiconductors, PCA9703PW,118 Datasheet - Page 5

• Manufacturer Part Number: PCA9703PW,118
• Description: IC SHIFT REG SPI GPI 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9703PW,118

• Package / Case: 24-TSSOP
• Applications: Automotive
• Interface: SPI Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: PCA
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 5 V
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Frequency: 5 MHz
• Mounting Style: SMD/SMT
• Output Current: 6 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5114-2; PCA9703PW,118

NXP Semiconductors
7. Functional description
PCA9703_1
Product data sheet
PCA9703 is a 16-bit General Purpose Input (GPI) with an open-drain interrupt output
designed to monitor switch status. By putting an external 100 kΩ series resistor at the
input port, the device allows the input to tolerate momentary double 12 V battery, reverse
battery, 27 V jump start or 40 V load dump conditions. The interrupt output is asserted
when an input port status changes, the input is not masked and the interrupt output is
enabled. The open-drain interrupt output is enabled when INT_EN is HIGH and disabled
when INT_EN is LOW. The INT_EN also enables the GPI pins when it is HIGH. In cyclic
pull-up applications the GPI pull-ups should be active before the INT_EN is taken HIGH
and the INT output should only be sampled after transient conditions have settled.
Additionally, interrupts can be disabled in software by using the interrupt mask feature.
The input port status is accessed via the 4-wire SPI interface.
Upon power-up, the power-up reset cell clears all the registers, resulting in all zeros in
both the input status register and the interrupt mask register. Since a zero in the interrupt
mask register masks the interrupt from that pin, there will not be any interrupts generated.
After power-up it is necessary to access the PCA9703 through the SPI pins in order to
activate the interrupt for any GPI pins. When the PCA9703 is read over the SPI wires, the
input conditions are clocked into the input status register on the CS falling edge. Since the
inputs and the input status register now match, no interrupt is generated and any
pre-existing interrupt is cleared. The input status register data is parallel loaded into the
shift register on the first rising edge of the SCLK. The serial input data is captured on the
opposite clock edge so that there is a
diminished by the propagation time so the SCLK falling edge to rising edge must be long
enough to provide sufficient set-up time. Successive clock cycles on the SCLK pin clock
the data out of the PCA9703 and new data from the SDIN into the shift register. There is
no limit to the number of clock cycles that can be applied with the CS LOW, however
sufficient clock cycles should be used to both shift out all of the GPI data and shift in the
new interrupt mask data to the correct position with the MSB first before the CS rising
edge.
For cyclic switch bias applications the switch bias should be applied first, then after the
input voltage is settled the general purpose inputs are switched on by taking the INT_EN
HIGH. This also enables the interrupt output, which will only indicate an interrupt if the GPI
data does not match the input status register on a bit that is enabled by the interrupt mask
register value. If an interrupt is generated, the pull-up should remain active and the
INT_EN should remain active and the SPI pins are used to update the input status register
and read the data out. They are also used to store the new interrupt mask on the rising
edge of CS. After the SPI transaction is complete the INT_EN is taken LOW to turn the
inputs off and disable the INT output. Then the GPI pull-ups can be turned off. The GPI
pins are specifically designed so that any ESD/overstress current flows to ground, not
V
value after pull-up cycling as before the input pull-up cycling, before the input is enabled it
will be detected as the same state.
If the V
move down since they are a function of the V
interrupt mask register retain their values to below V
be used to generate a power-up reset if the V
operating range.
DD
. They are also specifically designed so that if the input voltage returns to the same
DD
falls below the 4.5 V minimum specified supply voltage, the input threshold will
Rev. 01 — 23 February 2010
1
⁄
2
18 V tolerant SPI 16-bit GPI with maskable INT
clock cycle hold time. The set-up time is
DD
DD
voltage. The input status register and the
falls below 0.2 V before returning to the
DD
= 2.0 V and power-down can only
PCA9703
© NXP B.V. 2010. All rights reserved.
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