pca9703 NXP Semiconductors, pca9703 Datasheet
pca9703
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pca9703 Summary of contents
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... The input level is recognized as a HIGH when it is greater than 0.8 × V LOW threshold of 2 node). The PCA9703 can monitor switch inputs. The falling edge of the CS pin samples the input port status and clears the interrupt. When CS is LOW, the rising edge of the SCLK loads the shift register and shifts the value out of the shift register ...
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... PCA9703HF 9703 PCA9703PW PCA9703PW TSSOP24 [1] PCA9703PW/Q900 PCA9703PW TSSOP24 [1] PCA9703PW/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP. PCA9703_1 Product data sheet 18 V tolerant SPI 16-bit GPI with maskable INT Package Name Description HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 × 4 × 0.75 mm plastic thin shrink small outline package ...
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... NXP Semiconductors 5. Block diagram IN0 INPUT IN1 INPUT IN15 INPUT Fig 1. Block diagram of PCA9703 6. Pinning information 6.1 Pinning terminal 1 index area Fig 2. Pin configuration for HWQFN24 PCA9703_1 Product data sheet V DD PCA9703 DFF0 DFF1 DFF15 INPUT STATUS REGISTER V SS IN0 IN1 ...
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... Rev. 01 — 23 February 2010 PCA9703 Description 3-state serial data output; normally high-impedance open-drain interrupt output (active LOW) GPI pin enable and interrupt output enable 1 = GPI pin and interrupt output are enabled 0 = GPI pin and interrupt output are disabled and ...
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... Successive clock cycles on the SCLK pin clock the data out of the PCA9703 and new data from the SDIN into the shift register. There is no limit to the number of clock cycles that can be applied with the CS LOW, however ...
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... SPI bus operation The PCA9703 interfaces with the controller via the 4-wire SPI bus that is comprised of the following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial data out (SDOUT). To access the device, the controller asserts CS LOW, then sends SCLK and SDIN ...
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... PCA9703_1 Product data sheet 18 V tolerant SPI 16-bit GPI with maskable INT sample SDIN MSB − MSB in MSB − 1 out MSB out DATA[15:0] DATA[15:0] Rev. 01 — 23 February 2010 PCA9703 LSB in LSB out 002aae286 © NXP B.V. 2010. All rights reserved ...
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... – Rev. 01 — 23 February 2010 18 V tolerant SPI 16-bit GPI with maskable INT [1] [2] INT output Mask bit = 1 (unmasked Equation 1 PCA9703 Mask bit = 0 (masked (1) © NXP B.V. 2010. All rights reserved ...
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... V tolerant SPI 16-bit GPI with maskable INT HIGH LOW 002aae101 and 4.5 V the voltage DD . This means that if the user applies 3 4.5 V. This means there will always DD PCA9703 hysteresis minimum = 0.04V DD possible ground shift . This means DD © NXP B.V. 2010. All rights reserved ...
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... V 100 kΩ IN1 180 V PCA9703 open 500 kΩ IN2 50 kΩ kΩ IN15 V SS Rev. 01 — 23 February 2010 PCA9703 kΩ INT CS CONTROLLER SCLK OR SDIN PROCESSOR SDOUT INT_EN 002aae026 © NXP B.V. 2010. All rights reserved ...
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... For more information on SBC, refer to http://www.nxp.com/index.html#/pip/pip=[pfp=53482]|pp=[t=pfp,i=53482]. 8.2.1.1 UJA106x with PCA9703, standby Fig 7. • PCA9703 fits to SBC UJA106x and UJA107x family • PCA9703 can be powered SBC • Extends the SBC with 16 additional wake inputs μC can be set to stop-mode during standby to save ECU standby current. SBC with • ...
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... PCA970x supplied out of cyclically biased transistor regulator PCA9703_1 Product data sheet V IN0 IN1 PCA9703 IN15 UJA106x with PCA9703 with unsupplied μC (sleep) Rev. 01 — 23 February 2010 18 V tolerant SPI 16-bit GPI with maskable INT alternate alternate PVR100AD-B5V0 PMEM4010ND DD INT_EN INT ...
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... NXP Semiconductors 8.2.1.3 UJA107x with PCA9703, standby and sleep Fig 9. 1 kΩ Fig 10. UJA107x with PCA9703 with supplied μC (sleep) • UJA107x SBC provides WBIAS pin for cyclic biasing of the inputs • Compatible with UJA107x based ASSPs PCA9703_1 Product data sheet V1 1 kΩ ...
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... V tolerant SPI 16-bit GPI with maskable INT BAT BAT IN0 IN1 PCA9703 IN15 cyclic biasing Min −0.5 [1] - −0.5 [1] −0.5 −65 - for series resistor requirements. PCA9703 switch bias 002aae031 Max Unit +6.0 V μA 350 + °C +150 °C 125 © NXP B.V. 2010. All rights reserved. ...
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... Typ 4.5 5.0 - 1.0 [1] - 1 [3] 0.04V - DD [ −1 - − 2 − 0. 4 −5 − PCA9703 Max Unit 5.5 V μA 2.5 2.2 V 0.55V μA 100 μA +1 μ μ 0. 5.5 V μ © NXP B.V. 2010. All rights reserved ...
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... V tolerant SPI 16-bit GPI with maskable INT Min Typ - - - Figure Figure Figure 200 t SPILAG dis(SDOUT) PCA9703 Max Unit 5 MHz 250 ns 500 ns 800 ns t h(SCLK) 002aac428 © NXP B.V. 2010. All rights reserved ...
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... V tolerant SPI 16-bit GPI with maskable INT POR CS SCLK SDOUT MSB out t POR timing POR CS INn STATE 0 INT_EN t v(INT) INT Rev. 01 — 23 February 2010 PCA9703 MSB − 1 002aad158 STATE 1 STATE 0 t v(INT rel(int) rel(int) 002aaf294 © NXP B.V. 2010. All rights reserved. 2 ...
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... I O PULSE DUT GENERATOR PULSE DUT GENERATOR PULSE DUT GENERATOR R T Rev. 01 — 23 February 2010 PCA9703 V DD open kΩ kΩ 002aac580 and t ) en(SDOUT) dis(SDOUT 002aac581 ) v(SDOUT kΩ ...
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... V tolerant SPI 16-bit GPI with maskable INT detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9703 SOT355 θ (1) θ 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2010. All rights reserved ...
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... REFERENCES JEDEC JEITA - - - MO-220 Rev. 01 — 23 February 2010 18 V tolerant SPI 16-bit GPI with maskable INT detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION PCA9703 SOT994-1 c ISSUE DATE 07-02-07 07-03-03 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PCA9703_1 Product data sheet 18 V tolerant SPI 16-bit GPI with maskable INT Rev. 01 — 23 February 2010 PCA9703 © NXP B.V. 2010. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 21. Rev. 01 — 23 February 2010 PCA9703 Figure 21) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2010. All rights reserved. ...
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... Most Significant Bit Printed-Circuit Board Production Part Approval Process Resistor-Capacitor network System Basis Chip Serial Peripheral Interface microcontroller Rev. 01 — 23 February 2010 18 V tolerant SPI 16-bit GPI with maskable INT peak temperature PCA9703 time 001aac844 © NXP B.V. 2010. All rights reserved ...
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... Table 10. Revision history Document ID Release date PCA9703_1 20100223 PCA9703_1 Product data sheet 18 V tolerant SPI 16-bit GPI with maskable INT Data sheet status Change notice Product data sheet - Rev. 01 — 23 February 2010 PCA9703 Supersedes - © NXP B.V. 2010. All rights reserved ...
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... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Rev. 01 — 23 February 2010 PCA9703 © NXP B.V. 2010. All rights reserved ...
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... Product data sheet 18 V tolerant SPI 16-bit GPI with maskable INT 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 23 February 2010 PCA9703 © NXP B.V. 2010. All rights reserved ...
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... Application design-in information . . . . . . . . . 10 8.1 General application 8.2 Automotive application . . . . . . . . . . . . . . . . . . 10 8.2.1 SBC wake port extension with cyclic biasing . 11 8.2.1.1 UJA106x with PCA9703, standby 8.2.1.2 UJA106x with PCA9703, sleep 8.2.1.3 UJA107x with PCA9703, standby and sleep . 13 8.2.2 Application examples including switches to battery Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 16 12 Test information ...