pca9703 NXP Semiconductors, pca9703 Datasheet - Page 6

• Manufacturer Part Number: pca9703
• Description: 18 V Tolerant Spi 16-bit Gpi With Maskable Int
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA9703_1
Product data sheet
7.1.1 CS - chip select
7.1.2 SCLK - serial clock input
7.1.3 SDIN - serial data input
7.1.4 SDOUT - serial data output
7.1.5 Register access timing
7.1 SPI bus operation
Multiple PCA9703 devices can be serially connected for monitoring a large number of
switches by connecting the SDOUT of one device to the SDIN of the next device. SCLK
and CS must be common among all devices and interrupt outputs may be tied together.
No external logic is necessary because all the devices’ interrupt outputs are open-drain
that function as ‘wired-AND’ and can simply be connected together to a single pull-up
resistor.
The PCA9703 interfaces with the controller via the 4-wire SPI bus that is comprised of the
following signals: chip select (CS), serial clock (SCLK), serial data in (SDIN), and serial
data out (SDOUT). To access the device, the controller asserts CS LOW, then sends
SCLK and SDIN. When reading is complete and the interrupt mask data is in place, the
controller de-asserts CS. See
The CS pin is the device chip select and is an active LOW input. The falling edge of CS
captures the input port status in the input status register. If the interrupt output is asserted,
the falling edge of CS will clear the interrupt. When CS is LOW, the SPI interface is active.
When CS transitions HIGH the interrupt mask is stored and when CS is HIGH, the SPI
interface is disabled.
SCLK is the serial clock input to the device. It should be LOW and remain LOW during the
falling and rising edge of CS. When CS is LOW, the first rising edge of SCLK parallel
loads the shift register from the input status register. The subsequent rising edges on
SCLK serially shifts data out from the shift register. The falling edge of SCLK samples the
data on SDIN.
SDIN is the serial data input port. The data is sampled into the shift register on the falling
edge of SCLK. SDIN is only active when CS is LOW. This input has a 20 μA pull-down
current source to prevent the SDIN node from floating when CS is HIGH.
SDOUT is the serial data output signal. SDOUT is high-impedance when CS is HIGH and
switches to low-impedance after CS goes LOW. When CS is LOW, after the first rising
edge of SCLK the most significant bit in the shift register is presented on SDOUT.
Subsequent rising edges of SCLK shift the remaining data from the shift register onto
SDOUT.
Figure 4
LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input
status register, and subsequently the first rising edge of SCLK parallel loads the shift
register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift
register is valid and available on the SDOUT after the first rising edge of SCLK.
shows the waveforms of the device operation. Initially CS is HIGH and SCLK is
Rev. 01 — 23 February 2010
Figure 4
for register access timing.
18 V tolerant SPI 16-bit GPI with maskable INT
PCA9703
© NXP B.V. 2010. All rights reserved.
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