PCA9547D,118 NXP Semiconductors, PCA9547D,118 Datasheet

IC MUX 8CH I2C BUS 24SOIC

PCA9547D,118

Manufacturer Part Number
PCA9547D,118
Description
IC MUX 8CH I2C BUS 24SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9547D,118

Package / Case
24-SOIC (7.5mm Width)
Applications
Translating Multiplexer
Interface
I²C, SMBus
Voltage - Supply
2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Product
Decoders, Encoders, Multiplexers & Demultiplexers
Number Of Lines (input / Output)
8.0 / 1.0
Propagation Delay Time
0.3 ns at 2.3 V to 5.5 V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
1.0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935280788118
PCA9547D-T
PCA9547D-T
1. General description
2. Features
The PCA9547 is an octal bidirectional translating multiplexer controlled by the I
The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one
SCx/SDx channel can be selected at a time, determined by the contents of the
programmable control register. The device powers up with Channel 0 connected, allowing
immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of
the downstream I
I
that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the V
limit the maximum high voltage which will be passed by the PCA9547. This allows the use
of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C-bus state machine causing all the channels to be deselected, except Channel 0 so
PCA9547
8-channel I
Rev. 03 — 10 July 2009
1-of-8 bidirectional translating multiplexer
I
Active LOW RESET input
3 address pins allowing up to 8 devices on the I
Channel selection via I
Power-up with all channels deselected except Channel 0 which is connected
Low R
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO24, TSSOP24, HVQFN24
2
C-bus interface logic; compatible with SMBus standards
on
multiplexers
2
C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
2
C-bus multiplexer with reset
2
C-bus, one channel at a time
2
C-bus
DD
Product data sheet
pin can be used to
2
C-bus.

Related parts for PCA9547D,118

PCA9547D,118 Summary of contents

Page 1

PCA9547 8-channel I Rev. 03 — 10 July 2009 1. General description The PCA9547 is an octal bidirectional translating multiplexer controlled by the I The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one SCx/SDx channel ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Type number PCA9547D PCA9547PW PCA9547BS 3.1 Ordering options Table 2. Type number PCA9547D PCA9547PW PCA9547BS PCA9547_3 Product data sheet Ordering information Package Name Description SO24 plastic small outline package; 24 leads; body width 7.5 mm TSSOP24 plastic thin shrink small outline package; 24 leads; ...

Page 3

... NXP Semiconductors 4. Block diagram PCA9547 SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 RESET SCL SDA Fig 1. Block diagram of PCA9547 PCA9547_3 Product data sheet SWITCH CONTROL LOGIC RESET CIRCUIT 2 INPUT I C-BUS FILTER CONTROL Rev. 03 — ...

Page 4

... NXP Semiconductors 5. Pinning information 5.1 Pinning RESET Fig 2. Fig 4. PCA9547_3 Product data sheet SDA 3 22 SCL 4 21 SD0 SC0 SC7 SD1 6 19 SD7 PCA9547D SC1 7 18 SC6 8 17 SD2 SD6 SC2 9 16 SC5 SD3 10 15 SD5 SC3 11 14 SC4 SD4 SS 002aaa958 Pin confi ...

Page 5

... NXP Semiconductors 5.2 Pin description Table 3. Symbol A0 A1 RESET SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 V SS SD4 SC4 SD5 SC5 SD6 SC6 SD7 SC7 A2 SCL SDA V DD [1] HVQFN24 package die supply ground is connected to both the and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...

Page 6

... NXP Semiconductors 6. Functional description 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9547 is shown in internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. ...

Page 7

... NXP Semiconductors Table 4. Write = channel selection; Read = channel status 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of t register and I RESET input must be connected to V 6.4 Power-on reset ...

Page 8

... NXP Semiconductors 6.5 Voltage translation The pass gate transistors of the PCA9547 are constructed such that the V be used to limit the maximum voltage that will be passed from one I (1) maximum (2) typical (3) minimum Fig 7. Figure 7 PCA9547 is only tested at the points specified in data sheet). In order for the PCA9547 to act as a voltage translator, the V should be equal to, or lower than the lowest bus voltage ...

Page 9

... NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 10

... NXP Semiconductors 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL ...

Page 11

... NXP Semiconductors 7.4 Bus transactions Data is transmitted to the PCA9547 control register using the Write mode as shown in Figure 12. SDA Fig 12. Write control register Data is read from PCA9547 using the Read mode as shown in SDA Fig 13. Read control register PCA9547_3 Product data sheet slave address ...

Page 12

... NXP Semiconductors 8. Application design-in information 2 I C-bus/SMBus master Fig 14. Typical application PCA9547_3 Product data sheet SDA SDA SCL SCL RESET Rev. 03 — 10 July 2009 2 8-channel I C-bus multiplexer with reset SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 PCA9547 SD4 ...

Page 13

... NXP Semiconductors 9. Limiting values Table 5. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol tot T stg T amb [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C ...

Page 14

... NXP Semiconductors 10. Static characteristics Table 6. Static characteristics +85 C; unless otherwise specified. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage ...

Page 15

... NXP Semiconductors Table 7. Static characteristics +85 C; unless otherwise specified. See SS amb Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current ...

Page 16

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t LOW period of the SCL clock LOW t HIGH period of the SCL clock ...

Page 17

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 15. Definition of timing on the I SCL SDA RESET 50 % Fig 16. Definition of RESET timing PCA9547_3 Product data sheet HD;DAT HIGH SU;DAT 2 C-bus START rec(rst) Rev. 03 — 10 July 2009 PCA9547 2 8-channel I C-bus multiplexer with reset ...

Page 18

... NXP Semiconductors 12. Package outline SO24: plastic small outline package; 24 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 19

... NXP Semiconductors TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 22

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 23

... NXP Semiconductors Fig 20. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 11. Acronym CDM ESD HBM 2 I C-bus LSB MM PCB SMBus PCA9547_3 Product data sheet ...

Page 24

... PCA9547_3 20090710 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 5 “Limiting to “... should not exceed 125 C.” ...

Page 25

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 26

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 6 6.3 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 Power-on reset ...

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