BR24L02NUX-WTR Rohm Semiconductor, BR24L02NUX-WTR Datasheet - Page 10

• Manufacturer Part Number: BR24L02NUX-WTR
• Description: IC EEPROM 2KBIT 100KHZ VSON8
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of BR24L02NUX-WTR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UFDFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

●Write Command
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
○Write cycle
SDA
LINE
SDA
LINE
S D A
L IN E
S D A
L IN E
・As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W)
・As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word
Note)
Fig.40 Difference of slave address of each type
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.)
word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W,
after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the
address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data
up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written.
address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
S
A
R
T
T
S
T
A
R
T
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
Fig.37 Byte write cycle (BR24L32/64-W)
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
Fig.39 Page write cycle (BR24L32/64-W)
S
A
R
T
T
S
A
R
T
T
1 0
1
1
1 0
A D D R E S S
0
0
1
S L A V E
A D D R E S S
1
0
ADDRESS
1
1
N o te )
ADDRESS
S L A V E
N ote )
A 2
SLAVE
SLAVE
0
0
0
1 0
Note)
Note)
A 1
A2
A2
A 2
A 0
A1
A1
A 1
W
W
R
T
E
R
I
/
A0
A 0
A0
C
A
K
1
W
R
W
W
W
R
R
T
E
/
W
R
*
R
/
I
T
E
/
I
W
R
T
E
I
A D D R E S S (n )
*
0
C
A
C
K
A
K
C
A
K
1 st W O R D
*
W A
*1
WA
*1
*1 *2 *3
*1
W A
1 2
A 2
*
7
7
W A
11
*
1st WORD
ADDRESS
A D D R E S S (n )
A 1
*
ADDRESS
WA
W O R D
A 0
12
WORD
*1
WA
11
A
C
K
W A
A D D R E S S (n )
WA
0
2 n d W O R D
0
A
C
K
C
A
K
A
C
K
D 7
D7
D A TA (n )
W A
0
2nd WORD
ADDRESS
A
C
K
DATA
D 7
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
D A T A (n )
D 0
D0
WA
0
A
C
K
A
C
K
A
C
K
D 0
S
T
O
P
D7
10/40
D A TA (n +1 5 )
A
C
K
: Up to 16bytes (BR24L04-W, BR24L08-W,BR24L16-W)
: Up to 32bytes (BR24L32-W, BR24L64-W)
DATA
D A TA (n + 3 1 )
D 0
*2
A
C
K
D0
D 0
S
O
P
T
A
C
K
A
C
K
S
O
P
T
S
O
P
T
*1 As for WA7, BR24L01A-W becomes Don’t care.
*1 As for WA7, BR24L01A-W becomes Don’t care.
*2 As for BR24L01A/02-W becomes (n+7).
*1 As for WA12, BR24L32-W becomes Don’t care.
*1 As for WA12, BR24L32-W becomes Don’t care.
Technical Note
2009.09 - Rev.D