BR24L02NUX-WTR Rohm Semiconductor, BR24L02NUX-WTR Datasheet - Page 23

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BR24L02NUX-WTR

Manufacturer Part Number
BR24L02NUX-WTR
Description
IC EEPROM 2KBIT 100KHZ VSON8
Manufacturer
Rohm Semiconductor
Series
-r
Datasheet

Specifications of BR24L02NUX-WTR

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
BR24L02NUX-WTR
Manufacturer:
ROHM
Quantity:
50 000
Part Number:
BR24L02NUX-WTR
Manufacturer:
ROHM/罗姆
Quantity:
20 000
●Sync data input/output timing
●Block diagram
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
○At write execution, in the area from the D0 taken clock rise of the first
○By setting WP "HIGH" in the area, write can be cancelled.
(Output)
(Input)
SCL
SDA
SCL
SDA
(入力)
SDA
(出力)
SCL
SDA
WP
DATA(1), to tWR, set WP= 'LOW'.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
WRITE DATA(n)
D1
tHD:STA
Fig.1-(a) Sync data input / output timing
tBUF
DATA(1)
Fig.1-(e) WP timing at write cancel
D0
GND
*2
*2
D0
*2
A0
A1
A2
Fig.1-(c) Write cycle timing
ACK
ACK
tR
1
2
3
4
tSU:DAT
CONDITION
tHIGH:WP
STOP
1
DATA(n)
tPD
tF
10bit: BR24S08-W
11bit: BR24S16-W
12bit: BR24S32-W
13bit: BR24S64-W
14bit: BR24S128-W
15bit: BR24S256-W
tLOW
High voltage
generating circuit
t
tHIGH
WR
Adddress
decoder
CONDITION
START
tDH
ACK
10bit
11bi t
12bit
13bit
14bit
15bit
tHD:DAT
*1
Control circuit
tWR
*1
tWR
8Kbit~256Kbit EEPROM array
10bit
11bit
12bit
13bit
14bit
15bit
START
Fig.2 Block diagram
2 A0, A1= Don’t use: BR24S08-W
Power source
voltage detection
A0, A1, A2= Don’t use: BR24S16-W
Slave - word
address register
STOP
23/40
SCL
SDA
WP
SCL
SDA
ACK
D1
DATA(1)
tSU:WP
Fig.1-(d) WP timing at write execution
tSU:STA
D0
Fig.1-(b) Start - stop bit timing
Data
register
8bit
ACK
tHD:STA
START BIT
DATA(n)
8
7
6
5
tSU:STO
SDA
Vcc
WP
SCL
ACK
Stop condition
ストップコンディション
Technical Note
2009.09 - Rev.D
tWR
STOP BIT
tHD:WP

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