BR24L02NUX-WTR Rohm Semiconductor, BR24L02NUX-WTR Datasheet - Page 9

• Manufacturer Part Number: BR24L02NUX-WTR
• Description: IC EEPROM 2KBIT 100KHZ VSON8
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of BR24L02NUX-WTR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UFDFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
www.rohm.com
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○Start condition (Start bit recognition)
○Stop condition (stop bit recongnition)
○Acknowledge (ACK) signal
○Device addressing
C BUS communication
2
I
and acknowledge is always required after each byte. I
connected by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is
PS, P0～P2 are page select bits.
Note) Up to 4 units BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected.
C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
'HIGH' is necessary.
satisfied, any command is executed.
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
bus according to the number of device addresses.
as shown below.
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Type
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
SDA
SCL
START
condition
S
1 0 1 0 A2 A1 A0 R/W
1 0 1 0 A2 A1 A0 R/W
1 0 1 0 A2 A1 PS R/W
1 0 1 0 A2 P1 P0 R/W
1 0 1 0 P2 P1 P0 R/W
1 0 1 0 A2 A1 A0 R/W
1 0 1 0 A2 A1 A0 R/W
ADDRESS
1-7
R/W
8
Fig.35 Data transfer timing
Slave address
ACK
9
2
1-7
C BUS carries out data transmission with plural devices
9/40
DATA
8
ACK
9
―
―
―
―
―
―
―
Maximum number of
connected buses
1-7
DATA
8
8
8
4
2
1
8
8
ACK
9
condition
STOP
P
Technical Note
2009.09 - Rev.D