MT18JSF51272PDZ-1G6M1 Micron Technology Inc, MT18JSF51272PDZ-1G6M1 Datasheet - Page 4

• Manufacturer Part Number: MT18JSF51272PDZ-1G6M1
• Description: MODULE DDR3 SDRAM 4GB 240RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18JSF51272PDZ-1G6M1

• Memory Type: DDR3 SDRAM
• Memory Size: 4GB
• Speed: 1600MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Descriptions
Table 6: Pin Descriptions
PDF: 09005aef83d9afa1
js-z-f18c256_512x72pdz.pdf – Rev. D 9/10 EN
RAS#, CAS#, WE#
Symbol
RESET#
DQSx#
Par_In
DQSx,
ODTx
CKx#
CKEx
DMx
CKx,
DQx
BAx
SAx
CBx
Sx#
SCL
Ax
(LVCMOS)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I
Check bits: Used for system error detection and correction.
Data input/output: Bidirectional data bus.
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
2
C bus.
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Pin Descriptions
2
C bus.