LM41CIMTX/NOPB National Semiconductor, LM41CIMTX/NOPB Datasheet - Page 13

• Manufacturer Part Number: LM41CIMTX/NOPB
• Description: IC HARDWARE MONITOR 14-TSSOP
• Manufacturer: National Semiconductor

Specifications of LM41CIMTX/NOPB

• Applications: Monitors
• Interface: 1-Wire
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 14-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM41CIMTX

1.0 Functional Description
1.3.4 Read and Write Transaction Exceptions
This section describes master and LM41 handling of special
bus conditions, encountered during either Read or Write
transactions.
If an LM41 receives a Start Bit in the middle of a transaction,
it aborts the current transaction (the LM41 does not "com-
plete" the current transaction) and begins a new transaction.
Although not recommend for SensorPath normal operation,
this situation is legitimate, therefore it is not flagged as an
error by the LM41 and Attention Request is not generated in
response to it. The master generating the Start Bit, is re-
sponsible for handling the not "complete" transaction at a
"higher level".
If LM41 receives more than the expected number of data bits
(defined by the size of the accessed register), it ignores the
unnecessary bits. In this case, if both master and LM41
identify correct EP and ACK bits they "complete" the trans-
action. However, in most cases, the additional data bits differ
from the correct EP and ACK bits. In this case, both the
master and the LM41 do not "complete" the transaction. In
addition, the LM41 performs the following:
If the LM41 receives less than the expected number of data
bits (defined by the size of the accessed register), it waits
indefinitely for the missing bits to be sent by the master. If
then the master sends the missing bits, together with the
correct EP/ACK bits, both master and LM41 "complete" the
transaction. However, if the master starts a new transaction
• Data Bits This is the data written to the LM41 register,
• Even Parity (EP) This data bit is based on all preceding
• Acknowledge (ACK) During the write transaction the
• the BER bit in the LM41 Device Status register is set
• the LM41 generates an Attention Request
are driven by the master. Data is transferred serially with
the most significant bit first. The number of data bits may
vary from one address to another, based on the size of
the register in the LM41. This allows throughput optimi-
zation based on the information that needs to be written.
The LM41 supports 8-bit or 16-bit data fields, as de-
scribed in Section 2.0 "Register Set".
bits (Device Number, Internal Address, Read/Write and
Data bits) and the Even Parity bit itself. The parity (num-
ber of 1’s) of all the preceding bits and the parity bit must
be even - i.e. the result must be 0. During a write trans-
action, the EP bit is sent by the master to the LM41 to
allow the LM41 to check the received data before using it.
ACK bit is sent by the LM41 indicating to the master that
the EP was received and was found correct, and that no
conflict was detected on the bus (excluding Attention
FIGURE 6. Write Transaction, master write data to LM41
(Continued)
13
generating a Start Bit, the LM41 aborts the current transac-
tion (the LM41 does not "complete" the current transaction)
and begins the new transaction. The master is not notified by
the LM41 of the incomplete transaction.
1.3.5 Attention Request Transaction
Attention Request is generated by the LM41 when it needs
the attention of the master. The master and all LM41s must
monitor the Attention Request to allow bit re-sending in case
of simultaneous start with a Data Bit or Start Bit transfer.
Refer to the "Attention Request" section, Section 1.2.4 in the
"Bit Signaling" portion of the data sheet.
The LM41 will generate an Attention Request using the
following rules:
1. A Function event that sets the Status Flag has occurred
2. The "physical" condition for an Attention Request is met
3. At the first time 2 is met after 1 occurred, there has not
OR
1. A bus error event occurred, and
2. the "physical" condition for an Attention Request is met
3. At the first time 2. is met after 1 occurred, there has not
Request - see Section 1.3.5 "Attention Request Transac-
tion"). A write transfer is considered "completed" only
when the ACK bit is generated. A transaction that was not
positively acknowledged is not considered complete by
the LM41 (i.e. internal operation related to the transaction
are not performed) and the following are performed:
— The BER bit in the LM41 Device Status register is set;
— The LM41 generates an Attention Request before, or
A transaction that was not positively acknowledged is
also not considered "complete" by the master (i.e. inter-
nal operations related to the transaction are not per-
formed). The transaction may be repeated by the master,
after detecting the source of the Attention Request (the
LM41 that has a set BER bit in the Device Status regis-
ter). Note that the SensorPath protocol neither forces, nor
automates re-execution of the transaction by the master.
The values of the ACK bit are:
— 1: Data was received correctly;
— 0: An error was detected (no-acknowledge).
and Attention Request is enabled and
(i.e., the bus is inactive), and
been an Attention request on the bus since a read of the
Device Status register, or since a Bus Reset.
(i.e., the bus is inactive), and
been a Bus Reset.
together with the Start Bit of the next transaction
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