AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 13

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

6
Table 3
Pin or Ball
No.
PCI Interface
24
25
27
29
30
31
Data Sheet
Pin Description
Pin Definitions and Functions
Name
INTA#
RST#
PCI-CLK
GNT#
REQ#
PME#
Pin
Type
O/D
I
I
I
O
I/O
Buffer
Type
Function
PCI Interrupt Request
AN983B/BX asserts this signal when one of the interrupt
events occurs.
PCI Signal to Initialize the AN983B/BX
The active reset signal should be sustained at least 100µs
to guarantee that the AN983B/BX has completed the
initializing activity. During the reset period, all the output
pins of AN983B/BX will be set to tristate and all the O/D pins
are floated.
This PCI Clock Inputs to AN983B/BX for PCI Relative
Circuits as the Synchronized Timing Base with PCI Bus
The Bus signals are recognized on rising edge of PCI-CLK.
In order to let network operating properly, the frequency
range of PCI-CLK is limited between 20 MHz and 33 MHz
when network operating.
PCI Bus Granted
This signal indicates that the PCI bus request of
AN983B/BX has been accepted.
PCI Bus Request
Bus master device want to get bus access right
Power Management Event
The Power Management Event signal is an open drain,
active low signal. When WOL-bit 18 of CSR 18 be set into
“1”, means that the AN983B/BX is set into Wake On LAN
mode. In this mode, when the AN983B/BX receives a
Magic Packet frame from network then the AN983B/BX will
active this signal too.In the Wake On LAN mode, when
LWS-bit (bit 17) of CSR18 is set into “1” means the LAN-
WAKE signal is HP-style signal, otherwise it is IBM-style
signal.
13
Rev. 1.81, 2005-12-15
Pin Description
AN983B/BX