AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet
AN983B-BG-T-V8
Specifications of AN983B-BG-T-V8
SP000074652
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AN983B-BG-T-V8 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... AN983B/BX, PCI/Mini PCI-to-Ethernet LAN; PQFP - 128Pin Revision History: 2005-12-15, Rev. 1.81 Previous Version: Page/Date Subjects (major changes since last revision) 2000-10 Rev.0.1: Draft data sheet for review 2001-02 Rev.1.0: First release 2001-03 Rev.1.1: Add CSR15.bit28 MRXCK, Add CSR18.bit26 PMEP, Add CSR18.bit27 PMEPEN 2001-09 Rev ...
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... Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 General EEPROM Format Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Registers and Descriptors Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 AN983B/BX Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1.1 AN983B/BX Configuration Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 PCI Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2.1 PCI Control/Status Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 PHY Registers(Accessed by CSR9 MDI/MMC/MDO/MDC 9.3.1 PHY Transceiver Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9 ...
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... Table of Contents 12 Layout Guide (Rev. 1.0B 113 12.1 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.2 Trace Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 V 12.3 and GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 CC Data Sheet 5 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Receive Signal Timing Relations at the MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 23 MDIO Sourced by STA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 24 MDIO Sourced by PHY 110 Figure 25 Package outline for the AN983B / AN983BL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 26 Ground Via Trace Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 27 Power Trace Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 28 Ground Plane Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ...
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... Table 29 Flash Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 30 EEPROM Interface Timings (AC/AD 107 Table 31 Dimensions for 128 -pin PQFP Package (AN983B/ 111 Table 32 Dimensions for 128 -pin LQFP Package (AN983BLX 112 Table 33 Layout Guide Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Data Sheet 7 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detections. The AN983B/BX can be programmed as MAC-only controller. In this mode, it provides the standard MII interface to link to an external PHY. With this mode, it can be connected to the HomePNA PHY to support the HomePNA networking solution or Homeplug PHY (Power-line solution) to support Homeplug networking solution ...
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... Mbit/s and Link (keep on when link and 10 Mbit/s) – Activity (will be blinking with 10 Hz when receiving or transmitting but not collision) – FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding) Data Sheet 9 AN983B/BX Features Rev. 1.81, 2005-12-15 ...
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... Provides 128-pin QFP/LQFP packages for PCI/mini-PCI interfaces • 3.3 V power supply with 5 V/3.3 V I/O tolerance 4 Block Diagram CR/CSR/XR Registers PCI I/F Control Boot ROM I/F EEPROM I/F Figure 2 Block Diagram of the AN983B/BX Data Sheet DMA Power Management Control Control Transit Transmit FIFO MAC FIFO Loop-back Control Control ...
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... Vss-pci 32 AD31 33 AD30 34 AD29 35 AD28 36 Vdd-pci 37 AD27 38 Figure 3 Pin Assignment (top view) Data Sheet AN983B/AN983BL 11 AN983B/BX Pin Assignment Diagram 102 LED-Act 101 bra 3/Mdio bra 2/Mcrs 100 99 bra 1/Mcol 98 bra 0/Mrxerr PMEP 97 96 Vcc_detect 95 Vaux AD0 94 93 AD1 92 clk-run ...
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... Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high (identical to output with no type attribute). OD/PP Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with the OD attribute output with the PP attribute. ST Schmitt-Trigger characteristics TTL TTL characteristics Data Sheet Pin Assignment Diagram 12 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... The active reset signal should be sustained at least 100µs to guarantee that the AN983B/BX has completed the initializing activity. During the reset period, all the output pins of AN983B/BX will be set to tristate and all the O/D pins are floated. I This PCI Clock Inputs to AN983B/BX for PCI Relative Circuits as the Synchronized Timing Base with PCI Bus The Bus signals are recognized on rising edge of PCI-CLK ...
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... Multiplexed Address Data Pin of PCI Bus I/O Bus Command and Byte Enable I Initialization Device Select This signal is asserted when host issues the configuration cycles to the AN983B/BX. I/O Begin and Duration of Bus Access Driven by master device I/O Master Device is Ready to Data Transaction ...
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... BrD5/EDO 123 BrD6/EDI BrD7/ECK 124 EECS 125 BrCS# 114 BrOE# 115 BrWE# MII Interface (Program AN983B/BX as MAC-Only Mode,Set FCH [2:0] =100B) 127 Mdc Data Sheet Pin Buffer Function Type Type I/O OD Clock Run for PCI System In the normal operation situation, Host should assert this signal to indicate AN983B/BX about the normal situation ...
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... Differential Transmit Outputs The differential Transmit outputs of 100BASE-TX or 10BASE-T, these pins directly output to Magnetic. I Reference Bias Resistor To be tied to an external 10.0K (1%) resistor which should be connected to the analog ground at the other end. I Test Pin O 16 AN983B/BX Pin Description Rev. 1.81, 2005-12-15 ...
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... V when 3.3 Vaux support when 5 Vaux support from 3-way switch. I When this pin is asserted, it indicates PCI power source is supported. ACPI purpose, for detecting the main power is remained or not. This pin should be connected to PCI bus power source + AN983B/BX Pin Description Rev. 1.81, 2005-12-15 ...
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... Analog Power Pins 16 AAR AAREF V , 3.3 V AAT 8, 14, 19 GNDR, GNDREF, GNDT Data Sheet Pin Buffer Function Type Type O This signal is used as the WOL pin. It provides a programmable positive or negative pulse with approximately 50 ms width. Connect to 3 AN983B/BX Pin Description Rev. 1.81, 2005-12-15 ...
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... For networking operations the AN983B/BX transmits the data packet from transmit buffers in host memory to AN983B/BX’s transmit FIFO and receives the data packet from AN983B/BX’s receiving FIFO to receive buffers in host memory. The descriptors that the AN983B/BX supports to build in host memory are used as the pointers of these transmit and receive buffers. ...
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... Length 1 Buffer1 pointer Next point own --- Length 2 Buffer1 pointer Next point own --- Length 3 Buffer1 pointer Next point . . . 20 AN983B/BX Functional Descriptions Data Buffer Data Length 1 Data Length 2 Data Buffer Data Length 1 Data Buffer Data Length 2 Data Buffer Data Length Rev. 1.81, 2005-12-15 ...
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... Figure 7 Transmit Pointers for Descriptor Management • Receive Descriptor Pointers Data Sheet Descriptor 0 Data Buffer Length 2 Length 1 Buffer1 pointer Data Buffer2 pointer 1 Data Packet 1 1 Packet 1 1 Packet AN983B/BX Functional Descriptions Length 1 Length 2 Rev. 1.81, 2005-12-15 ...
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... Figure 8 Receive Pointers for Descriptor Management Data Sheet Descriptor 0 Data Buffer Packet Packet 1 0 Packet 2 22 AN983B/BX Functional Descriptions Rev. 1.81, 2005-12-15 ...
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... Transmit Scheme and Transmit Early Interrupt 7.3.1 Transmit Flow The flow of packet transmit is shown as below. AN983B read descriptor available descriptor(own=1) read data and put into tx fifo no deferring and greater than tx threshold DO TRANSMIT read the rest Figure 9 Transmit Flow 7.3.2 Transmit Pre-fetch Data Flow • ...
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... AN983B/BX Functional Descriptions IFG 2nd packet 1st packet is transmitted, check the 3rd packet handled by AN983B The saved time when transmit early interrupt is implemented handled by AN983B Rev. 1.81, 2005-12-15 ...
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... The size of 1st descriptor is program ed as the header size in advance the 1st the 2nd descriptor descriptor is full tim e 25 AN983B/BX Functional Descriptions finish time finish time handled by AN983B end of packet issue the second interrupt finish time Rev. 1.81, 2005-12-15 ...
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... When operating in 100BASE-TX mode the AN983B/BX detects a JK code for a preamble as well code for the packet end code is not detected, the AN983B/BX will abort this frame receiving and wait for a new JK code detection code is not detected, the AN983B/BX will report a CRC error. ...
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... Transceiver Operation In the transceiver portion of the AN983B/BX, it integrates the IEEE802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment) sub-layer, PMD (physical medium dependent) sub-layer for 100BASE-TX, the IEEE802.3 compliant functions of Manchester encoding/decoding, and transceiver for 10BASE-T. All the functions and operation schemes are described in the following sections. ...
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... NRZI to NRZ converter. In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receiving path. Data Sheet Functional Descriptions 28 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... When the Full Duplex mode and PAUSE function are selected after Auto-Negotiation completed, the AN983B/BX enables the PAUSE function for flow control of full duplex application. In this section we will describe how the AN983B/BX implements the PAUSE function. Data Sheet ...
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... Receive Operation for PAUSE Function Upon reception of a valid MAC Control frame, the AN983B/BX will start a timer for the length of time specified by the MAC Control Parameters field. When the timer value reaches zero then the AN983B/BX ends PAUSE state. ...
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... Figure 15 PAUSE Operation Receive State Diagram Data Sheet Functional Descriptions 31 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... There are two ways to reset the AN983B/BX. First, hardware reset, the AN983B/BX can be reset via RST pin. For ensuring proper reset operation, at least 100s active Reset input signal is required. Second, software reset, when bit 0 of CSR0 register is set to 1, the AN983B/BX will reset entire circuits and registers to default value then clear the bit 0 of CSR0 to 0. ...
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... Power States DO (Fully On) In this state the AN983B/BX operates as full functionality and consumes its normal power. While in the D0 state, if the PCI clock is lower than 16 MHz, the AN983B/BX may not receive or transmit frames properly this state the AN983B/BX doesn’t response to any accesses, except configuration space and full function context in place ...
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... D0 Data Sheet Clock Power Supported Actions to Function Stopped to – PCI Full speed configuration access (B0, B1) Stopped to – PCI Full speed configuration access (B0, B1) No clock No power Power-on reset 34 AN983B/BX Functional Descriptions Supported Actions from Function – – – Rev. 1.81, 2005-12-15 ...
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... PCI Subsystem Vendor ID MIN_GNT value. 0xFF MAX_LAT value. 0xFF CIS Pointer, it will be loaded into CR10. 0x0202 CSR18 (CR) bit 31-16 recall data. Please reference AN983B/BX Spec. Reserved, should be zero. Cardbus CIS length Reserved, should be zero. CheckSum, the least significant two bytes of FCS for data stored in offset 0.7D ...
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... Data Sheet AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex 100BaseTx Full Duplex 100BaseFx Full Duplex 36 AN983B/BX General EEPROM Format Description Rev. 1.81, 2005-12-15 ...
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... The PCI control/status registers are used to communicate between the host and AN983B/BX. Host can initialize, control, and read the status of the AN983B/BX through the mapped I/O or memory address space. Regarding the registers of transceiver portion of AN983B/BX, it includes 7 basic registers which are defined according to the clause 22 “Reconciliation Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mbit/s and 100 Mbit/s Auto-Negotiation on twisted pair” ...
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... Register is written by HW (register between input and output -> one cycle delay) write w read/write rwh Register can be modified by HW hardware affected rwv Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers End Address xxxx 0110 H H Dependency = . B 38 AN983B/BX Note Xxxxx Offset Address ...
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... Device ID* 04h Status 08h Base Class Code Subclass 0ch ------ ------ Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers Description Vendor ID* Command ----------- Latency timer Cache line size 39 AN983B/BX Description Software (SW) SW can only read this register SW can only read this register ...
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... Field Bits Type LDID 31:16 ro LVID 15:0 ro Reset Value loaded from EEPROM Configuration Command and Status Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers Subsystem vendor ID* Interrupt pin Driver Space Next_Item_Pt r PMCSR Offset 00 H Description Loaded Device ID The device ID number loaded from serial EEPROM. ...
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... Registers and Descriptors DescriptionAN983B/BX Configuration Registers Offset 04 H Description Status of Parity Error 1 , means that AN983B/BX detected a parity error. This bit will be set B in this condition even if the parity error response (bit 6 of CR1) is disabled. Status of System Error 1 , means that AN983B/BX asserted the system error pin ...
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... Command of Parity Error Response 0 , disable parity error response. AN983B/BX will ignore any B detected parity error and keep on its operating. Default value enable parity error response. AN983B/BX will assert system error B (bit 13 of CSR5) when a parity error is detected. Reserved Command of Master Operation Ability 0 ...
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... This value specifies the system cache line size in units of 32-bit double words (DW). The AN983B/BX supports 8, 16, and cache line size. This value is used by the AN983B/BX driver to program the cache alignment bits (bit 14 and 15 of CSR0). The cache alignment bits are used for cache oriented PCI commands ...
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... Subsystem ID and Vendor ID Note: Automatically recalled from EEPROM when PCI reset is deserted. SID_CR11 Subsystem ID and Vendor ID Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers Offset 14 H Description Memory Base Address This value indicates the base address of PCI control and status register (CSR0~28) ...
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... AN983B/BX supports up to 256 KB of boot ROM. Reserved Boot ROM Enable The AN983B/BX really enables its boot ROM access only if both the memory space access bit (bit 1 of CR1) and this bit are set enable Boot ROM (Combines with bit 1 of CR1) ...
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... AN983B/BX is connected.Always 01h: means the AN983B/BX connects to INTA# Interrupt Line This value indicates which of the system interrupt request lines the INTA# of AN983B/BX is routed to. The BIOS will fill this field when it initializes and configures the system. The AN983B/BX driver can use this value to determine priority and vector information. 46 ...
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... Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers Offset 40 H Description Reserved Driver Space for special purpose Since this area won’t be cleared in the software reset, the AN983B/BX driver can use this rw area for special purpose. Reserved Offset 80 H Description Device ID The device ID number of AN983B/BX ...
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... The AN983B/BX supports D1 Power Management State. Aux Current These three bits report the maximum 3.3 Vaux current requirements for AN983B/BX. If bit 31 of PMR0 is ‘1’, the default value is 0101b, means AN983B/BX need 100 mA to support remote wake- cold power state. Device Specific Initialization ...
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... This bit is set when the AN983B/BX would normally assert the PME# signal for wake-up event, this bit is independent of the state of the PME- En bit. Writing a “1” to this bit will clear it and cause the AN983B/BX to stop asserting a PME# (if enabled). Writing a “0” has no effect. ...
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... Read and Write clear Data Sheet Registers and Descriptors DescriptionAN983B/BX Configuration Registers 50 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Multicast Address Register 0 MAR1_CSR28 Multicast Address Register 1 UAR0_CSR_29 Unicast Address Register 0 UAR1_CSR_30 Unicast Address Register 1 OMR Operation Mode Register The register is addressed wordwise. Standard abbreviations: Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers End Address 0000 00FC AN983B/BX Note Offset Address Page Number ...
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... SW can read the register, with write mask the register can be cleared SW can read and write this register Register is read and writable by SW Writing to the register generates a strobe signal for the HW (1 pdi clock cycle) Register is read and writable by SW. 52 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Memory Read Line Enable Note: rw*: Before writing the transmitting and receiving operations should be stopped enable AN983B/BX to generate memory read line command while B read access instruction reach the cache line boundary. If the read access instruction doesn’t reach the cache line boundary then AN983B/BX uses the memory read command instead ...
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... transmit higher priority B Software Reset Note: rw*: Before writing the transmitting and receiving operations should be stopped reset all internal hardware except configuration registers. This B signal will be cleared by AN983B/BX itself after it completed the reset process. Offset AN983B/BX Reset Value FFFF FFFF H Rev. 1.81, 2005-12-15 ...
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... Registers and Descriptors DescriptionPCI Control/Status Registers Description Transmit Poll Demand When written any value in suspended state, trigger read-tx-descriptor process and check the own-bit, if own-bit = 1, then start transmit process. Note: rw*: Before writing the transmitting process should be in the suspended state. 55 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Note: rw*: Before writing the receiving process should be in the suspended state. Offset 18 H Description Start Address of Receive Descriptor Note: rw*: Before writing the receiving process should be stopped. Must be 00, DW Boundary 56 AN983B/BX Reset Value FFFF FFFF H Reset Value xxxx xxxx H Rev. 1.81, 2005-12-15 ...
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... This field is valid only when bit 13 of CSR5 (fatal bus error) is set. There is no interrupt generated by this field. 000 , parity error B 001 , master abort B 010 , target abort B 011 , reserved B 1xx , reserved B 57 AN983B/BX Reset Value xxxx xxxx H Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... Fatal Bus Error Note: lh: High Latching and cleared by writing while any of parity error master abort, or target abort is occurred B (see bits 25~23 of CSR5) AN983B/BX will disable all bus access. The way to recover parity error is by setting software reset. Reserved 58 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Note: lh: High Latching and cleared by writing 1 Receive Descriptor Unavailable Note: lh: High Latching and cleared by writing while the next receive descriptor can’t be applied by AN983B/BX. B The receive process is suspended in this situation. To restart the receive process the ownership bit of next receive descriptor should ...
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... Type TCI 0 ro/lh Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Description Transmit Completed Interrupt Note: lh: High Latching and cleared by writing means a frame transmission is completed while bit 31 of TDES1 B is asserted in the first transmit descriptor of the frame 60 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... B Reserved SQE Disable Note only write when the transmit processor stoppes enable SQE function for 10BASE-T operation. The AN983B/BX B provides SQE test function for 10BASE-T half duplex operation 1 , disable SQE function B Reserved Transmit Threshold Control Note only write when the transmit processor stoppes ...
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... Notice: In “Stop Receive” state the PAUSE packet and Remote Wake Up packet won’t be affected and can be received if the corresponding function is enabled receive processor will enter running state B Reserved Offset AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... CSR7 to enable transmit descriptor B unavailable interrupt Transmit Processor Stopped Interrupt Enable 1 , combine this bit and bit 15 of CSR7 to enable transmit processor B stopped interrupt Transmit Completed Interrupt Enable 1 , combine this bit and bit 16 of CSR7 to enable transmit completed B interrupt. 63 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Specified read data from the external PHY MII Management Control 0 , Write operation to the external PHY Read operation from the external PHY B MII Management Data Output Specified Write Data to the external PHY 64 AN983B/BX Reset Value 0000 0000 H Reset Value 0004 000E H Rev. 1.81, 2005-12-15 ...
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... Serial EEPROM Select Set together with CSR9 bit14 enable EEPROM access Reserved Serial EEPROM Data Out This bit serially shifts data from the EEPROM to the AN983B/BX. Serial EEPROM Data In This bit serially shifts data from the AN983B/BX to the EEPROM. Serial EEPROM Clock High/Low this bit to provide the clock signal for EEPROM ...
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... PMR1 after AN983B/BX has received a Magic packet. Link Status Changed Enable The AN983B/BX will include the “Link Status Changed” event into wake- up events. If this bit is set, AN983B/BX will assert PMES bit of PMR1 after AN983B/BX has detected a link status changed event. Reserved Wake-up Frame Received Note: rw1c: Read only and Write one cleared ...
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... Registers and Descriptors DescriptionPCI Control/Status Registers Description Magic Packet Received Note: rw1c: Read only and Write one cleared indicates AN983B/BX has received a magic packet cleared B by writing 1 or upon power-up reset not affected by a hardware or software reset Link Status Changed Note: rw1c: Read only and Write one cleared. ...
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... B Non-Jabber jabber expired re-enable transmit function after (100 Mbit/s) or 420 ms (10 Mbit/ immediately re-enable the transmit function after jabber expired B Jabber Disable 1 , disable transmit jabber function B 68 AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... Added Normal Interrupt Status Summary Note High Latching and cleared by writing any of the added normal interrupts happened B Added Abnormal Interrupt Status Summary Note High Latching and cleared by writing any of the added abnormal interrupt happened B Reserved 69 AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... AN983B/BX. B Receive process is suspended in this situation. To restart the receive process the ownership bit of the next receive descriptor should be set to AN983B/BX and a receive poll demand command should be issued (or a new recognized frame is received, if the receive poll demand is not issued). Receive Completed Interrupt ...
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... Description Transmit Descriptor Unavailable Note High Latching and cleared by writing while the next transmit descriptor can’t be applied by AN983B/BX. B The transmission process is suspended in this situation. To restart the transmission process the ownership bit of next transmit descriptor should be set to AN983B/BX and if the transmit automatic polling is not enabled then a transmit poll demand command should be issued ...
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... Receive Stopped Interrupt Enable 1 , combine this bit and bit 15 of CSR7 to enable receive stopped B interrupt Receive Descriptor Unavailable Interrupt Enable 1 , combine this bit and bit 15 of CSR7 to enable receive descriptor B unavailable interrupt 72 AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... H Description D3cold Support, Mapped to CR48<31> Aux Current These three bits report the maximum 3.3 Vaux current requirements for AN983B/BX. If bit 31 of PMR0 is ‘1’, the default value is 0101b, means AN983B/BX need 100 mA to support remote wake-up in D3cold power state. 73 AN983B/BX Reset Value ...
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... B Power Management Enables the AN983B/BX whether to activate the Power Management abilities. When this bit is set into “0” the AN983B/BX will set the Cap_Ptr register to zero, indicating no PCI compliant power management capabilities.The value of this bit will be mapped to NC-bit 20 of CR1.In PCI Power Management mode, the Wake-up events include “Wake-up Frame Received” ...
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... FIFO threshold selection in bit 3~2 of this B register, the receive threshold is set to 64-byte the receive FIFO threshold is enabled B Drain Receive Threshold bytes (8 DW bytes (16 DW store-and -forward reserved B Software Interrupt Automatically Transmit-underrun Recovery Enable 1 , enable automatically transmit-underrun recovery B 75 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... This bit is set when the AN983B/BX would normally assert the PME# signal for wake-up event, this bit is independent of the state of the PME- En bit. Writing a “1” to this bit will clear it and cause the AN983B/BX to stop asserting a PME# (if enabled). Writing a “0” has no effect. Since the AN983B/BX doesn’ ...
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... PME# assertion.This bit defaults to “0” if the function does not support PME# generation from D3cold. Reserved PowerState This two bit field is used both to determine the current power state of the AN983B/BX and to set the AN983B/BX into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 ...
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... The current working transmit descriptor pointer for driver’s double- checking or other special purpose. Offset 98 H Description Working Receive Descriptor Pointer The current working receive descriptor pointer for driver’s double- checking or other special purpose. 78 AN983B/BX Reset Value xxxx xxxx H Reset Value xxxx xxxx H Rev. 1.81, 2005-12-15 ...
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... LED pin – fd/col. Reserved Read Enable Clear if read data is ready in DATA, bit7-0 of FROM. Write Enable Cleared if write completed. Flash ROM Address Read/Write Data of Flash ROM 79 AN983B/BX Reset Value 0000 0000 H Reset Value 8000 0000 H Rev. 1.81, 2005-12-15 ...
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... PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17 = 000). Multicast Address Register 0 Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Offset A4 H Description Physical Address Byte Offset A8 H Description Reserved Reserved Physical Address Byte 5 Physical Address Byte 4 80 AN983B/BX Reset Value xxxx xxxx H Reset Value ?? H Rev. 1.81, 2005-12-15 ...
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... MAR0_CSR27 Multicast Address Register 0 Field Bits Type MAB3 31:24 rw MAB2 23:16 rw MAB1 15:8 rw MAB0 7:0 rw Data Sheet Registers and Descriptors DescriptionPCI Control/Status Registers Offset AC H Description Multicast Address Byte AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17 = 000). Multicast 64 Algorithm AN983B/BX uses CRC [5:0] to hit one of the 64 entries in UMAR1 [31:0] and MAR0[31:0] by generated CRC32 from Ethernet DA (destination address). The most significant bit CRC [5] chooses the upper or lower double word, (MAR1 or MAR0), the lower 5 bit presents for the corresponding bit inside the double word ...
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... H Description Unicast Address Byte 7 (hash table 63:56) Unicast Address Byte 6 (hash table 55:48) Unicast Address Byte 5 (hash table 47:40) Unicast Address Byte 4 (hash table 39:32) Offset AN983B/BX Reset Value 0000 0000 H Reset Value 0000 0000 H Reset Value 0000 0007 H Rev. 1.81, 2005-12-15 ...
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... Link on B Reserved EERLOD Write 1 and this bit will cause AN983B/BX to reload data from EEPROM. After reload completed, this bit will be cleared automatically. Reserved Operation Mode These three bits are used to configure AN983B/BX’s operation mode: 111b: Single Chip mode (Normal operation) At this mode, AN983B/BX is configured as single chip to provide PCI to Ethernet controller ...
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... Latch high signal at low-level, clear on self clearing read Latch high, lhmk Latch high signal at high level, register mask clearing cleared with written mask Data Sheet Registers and Descriptors DescriptionPHY Registers(Accessed by CSR9 End Address 0000 0006 AN983B/BX Note Offset Address Page Number ...
Page 86
... Loopback 0 , disable loopback enable loopback B 86 AN983B/BX Description Software (SW) SW can read the register, with write mask the register can be cleared (1 clears) SW can read the register SW can read the register SW can read the register, with write mask the register can be cleared ...
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... Mbit 100 Mbit/s B Autonegotiation Enable 0 , disable autoneg enable autoneg B Power Down 0 , normal operation Power Down B Isolate 0 , normal operation isolate PHY from MII B Restart Autonegotiation 1 , Restart Autoneg B Duplex Mode 0 , half duplex full duplex B Collision Test Not implemented Reserved 87 AN983B/BX Rev. 1.81, 2005-12-15 ...
Page 88
... PHY cannot accept management frames with preamble B suppression 1 , PHY can accept management frames with preamble suppression B Autoneg Complete 0 , autoneg incomplete autoneg completed B Remote Fault Note: lh: Latch High remote fault detected remote fault detected B 88 AN983B/BX Reset Value 7849 H Rev. 1.81, 2005-12-15 ...
Page 89
... PHY can auto-negotiate B Link Status Note: lh: Latch Low 0 , link is down link Jabber Detect Only used in 10Base-T mode. Read 100Base-TX mode. Note: lh: Latch High 1 , jabber condition detected B Extended Capability 0 , basic register set capabilities only extended register set capabilities B 89 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Offset 2 H Description PHY_ID[31-16] OUI (bits 3-18) Offset 3 H Description PHY_ID[15-10] OUI (bits 19-24) PHY_ID[9-4] Manufacturer’s Model Number (bits 5-0) PHY_ID[3-0] Revision Number (bits 3-0); Register 3, bit bit of PHY Identifier 90 AN983B/BX Reset Value 001D H Reset Value 2411 H Rev. 1.81, 2005-12-15 ...
Page 91
... Unit is capable of Full Duplex 10BASE-T B 10BASE-T Half Duplex Technology ability bit Unit is not capable of Half Duplex 10BASE Unit is capable of Half Duplex 10BASE-T B Selector Field Identifies the type of message being sent. Currently only one value is defined. 91 AN983B/BX Reset Value 0001 H Rev. 1.81, 2005-12-15 ...
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... Base Page is requested Link Partner is requesting Next Page function B Acknowledge Link Partner acknowledgement bit Remote Fault Link Partner is indicating a fault Technology Ability Link Partner technology ability field. Selector Field Link Partner selector field 92 AN983B/BX Reset Value 0000 0000 H Rev. 1.81, 2005-12-15 ...
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... Local device is Next Page Able B Page Received Note: lh: Latch Hight New Page has not been received New Page has been received B Link Partner Autonegotiation Able 0 , Link Partner is not Autonegotiation able Link Partner is Autonegotiation able B 93 AN983B/BX Reset Value 0004 H Rev. 1.81, 2005-12-15 ...
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... Latch high, lhmk Latch high signal at high level, register mask clearing cleared with written mask Latch low, llmk Latch high signal at low-level, register mask clearing cleared on read Data Sheet Registers and Descriptors DescriptionDescriptors and Buffer Management 94 AN983B/BX Offset Address Page Number 0Ch ...
Page 95
... Register is used as input for the HW, self clearing the register will be cleared due mechanism. 9.4.1 Receive Descriptor Descriptions The AN983B/BX provides receive and transmit descriptors for packet buffering and management. Descriptors and receive buffers addresses must be longword alignment Table 20 Receive Descriptor Table 31 ------------------------------------------------------------------------------------------------------------------------------ 0 ...
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... Ethernet type B Receive Watchdog (refer to CSR15, bit 4) This bit is valid only in last descriptor. Reserved Dribble Bit This bit is valid only in last descriptor. ECPacket length is not integer multiple of 8-bit. CRC Error This bit is valid only in last descriptor. 96 AN983B/BX Rev. 1.81, 2005-12-15 ...
Page 97
... Field Bits Type Data Sheet Registers and Descriptors DescriptionDescriptors and Buffer Management Description Overflow This bit is valid only in last descriptor. 97 AN983B/BX Rev. 1.81, 2005-12-15 ...
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... Use for chain structure. Indicates the buffer2 address is the next descriptor address.Ring mode takes precedence over chained mode Reserved Buffer 2 Size DW boundary Buffer 1 Size DW boundary Offset 08 H Description Receive Buffer Address 1 This buffer address should be double word aligned. 98 AN983B/BX Reset Value xxxx xxxx H Reset Value xxxx xxxx H Rev. 1.81, 2005-12-15 ...
Page 99
... RDES3 RDES3 Field Bits Type RBA2 31:0 rw 9.4.2 Transmit Descriptor Descriptions The AN983B/BX provides receive and transmit descriptors for packet buffering and management. Descriptor addresses must be longword alignment Table 21 Transmit Descriptor Table TDES0 Own Status TDES1 Control TDES2 Buffer1 address TDES3 ...
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... Interrupt Completed Last Descriptor First Descriptor Reserved Disable add CRC Function End of Ring 2nd Address Chain Indicates the buffer2 address is the next descriptor address Disable Padding Function Reserved Buffer 2 Size Buffer 1 Size 100 AN983B/BX Reset Value xxxx xxxx H Rev. 1.81, 2005-12-15 ...
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... Registers and Descriptors DescriptionDescriptors and Buffer Management Offset 08 H Description Buffer Address 1 Without any limitation on the transmission buffer address. Offset 0Ch H Description Buffer Address 2 Without any limitation on the transmission buffer address. 101 AN983B/BX Reset Value xxxx xxxx H Reset Value xxxx xxxx H Rev. 1.81, 2005-12-15 ...
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... CC I -10 – ilp V – – olp V V 0.9 – ohp – inp C 10 – clkp 102 AN983B/BX Electrical Specifications and Timings Unit Note / Test Condition Max. 3.6 V – 0 0 150 °C 70 °C 2000 V Unit Note / Test Condition Max. 3.6 V – ...
Page 103
... T 1 – – f Symbol Values Min. Typ – cyc T 12 – high T 12 – low – 1 – 103 AN983B/BX Electrical Specifications and Timings Unit Note / Test Condition Max. V 0.3 V – – CC µA 10 – 0.2 V – – V – – Unit Note / Test Condition Max. – ...
Page 104
... T 7 – (ptp) 10, 12 – – – rst T 100 – rst-clk T – – rst-off 104 AN983B/BX Electrical Specifications and Timings 0.4Vcc Unit Note / Test Condition Max – – – ns – – – ns – – ns – – ns – – ms – ...
Page 105
... Electrical Specifications and Timings Vth=2.4Vcc Vtl=0.4Vcc Tval (max=11ns) Toff 1.5V Unit Note / Test Condition Max. – ns – – – – – ns – – ns – – – – ns – – – ns – – ns – – ns – – ns – – ns – Rev. 1.81, 2005-12-15 AN983B/BX ...
Page 106
... Tas Tah Tfasc Tcs Twp 106 Electrical Specifications and Timings Unit Note / Test Condition Max. – ns – – ns – – ns – – ns – – ns – – ns – µs 200 – µs – – Twph Tds Tdh Rev. 1.81, 2005-12-15 AN983B/BX ...
Page 107
... T 160/640 – edts T 2320/ – edth 9280 T 7400/ – ecsl 29600 107 AN983B/BX Electrical Specifications and Timings Toe Toh Unit Note / Test Condition Max. V 0.4M/ Hz 2.7 V < CC 0.1M V – ns 2.7 V < – ns 2.7 V < ...
Page 108
... CS CLK DI Figure 20 Serial EEPROM Timing Data Sheet Tecss Tecsh Tedts Tedth 108 AN983B/BX Electrical Specifications and Timings Tecsl Rev. 1.81, 2005-12-15 ...
Page 109
... TXD<3:0>,TX_EN, TX_ER 0 ns Min 25 ns MAX Figure 21 Transmit Signal Timing Relationships at the MII RX_CLK RXD<3:0>,RX_DV, RX_ER Figure 22 Receive Signal Timing Relations at the MII Data Sheet Electrical Specifications and Timings 10 ns MIN 109 AN983B/BX V ih(min) V il(max) V ih(min) V il(max) V ih(min) V il(max) V ...
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... MDC MDIO Figure 23 MDIO Sourced by STA MDC MDIO 0 ns Min 300 ns MAX Figure 24 MDIO Sourced by PHY Data Sheet 10 ns MIN 110 AN983B/BX Electrical Specifications and Timings V ih(min) V il(max) V ih(min) V il(max MIN V ih(min) V il(max il(max) Rev. 1.81, 2005-12-15 ih(min) ...
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... Package Outlines E Figure 25 Package outline for the AN983B / AN983BL Table 31 Dimensions for 128 -pin PQFP Package (AN983B/X) Symbol Description A Overall Height A1 Stand Off b Lead Width c Lead Thickness D Terminal Dimension 1 D1 Package Body 1 E Terminal Dimension 2 E1 Package Body 2 e1 Lead Pitch ...
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... Table 32 Dimensions for 128 -pin LQFP Package (AN983BLX) Symbol Description A Overall Height A1 Stand Off b Lead Width c Lead Thickness D Terminal Dimension 1 D1 Package Body 1 E Terminal Dimension 2 E1 Package Body 2 e1 Lead Pitch L1 Foot Length T Lead Angle Y Coplanarity Data Sheet Minimum Maximum - 1 ...
Page 113
... GND. CC • Connect Pin 8 and pin 14 together first then use signal via to Gnd. Data Sheet Description Add Item 2-d to reduce receive CRC error. routing at other plane. 113 AN983B/BX Layout Guide (Rev. 1.0B) Rev. 1.81, 2005-12-15 ...
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... The isolation voltage of the transformer should be rated to be greater than 2 kV. V – The sample board and GND plane at below side. CC Data Sheet Bad Power Switch Power PLANE V and GND plane. CC 114 AN983B/BX Layout Guide (Rev. 1.0B) Good Power Switch AN983B VCC FROM PCI Good Rev. 1.81, 2005-12-15 ...
Page 115
... RJ45 Chassis Ground Figure 28 Ground Plane Arrangement Data Sheet VCC PLANE UNDER Transformer System Ground 115 AN983B/BX Layout Guide (Rev. 1.0B) CHIP Rev. 1.81, 2005-12-15 ...
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... Published by Infineon Technologies AG ...