AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 32

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

7.6
The AN983B/BX provides 2 kinds of LED display mode; the detailed descriptions about the operation are
described in the PIN Description section.
7.6.1
for
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7.6.2
for
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7.7
7.7.1
There are two ways to reset the AN983B/BX. First, hardware reset, the AN983B/BX can be reset via RST pin. For
ensuring proper reset operation, at least 100s active Reset input signal is required. Second, software reset, when
bit 0 of CSR0 register is set to 1, the AN983B/BX will reset entire circuits and registers to default value then clear
the bit 0 of CSR0 to 0.
7.7.2
When bit 15 of PHY register 0 is set to 1, the transceiver will reset entire circuits and register contents to default
value then clear the bit 15 of PHY register 0 to 0.
7.8
The AN983B/BX can assert a signal to wake up the system when it received a Magic Packet from the network.
The Wake on LAN operation is described as follow.
7.8.1
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7.8.2
The Wake on LAN enable function is controlled by bit 18 of CSR18; it is loaded from EEPROM after reset or
programmed by driver to enable Wake on LAN function. If the bit 18 of CSR18 is set and the AN983B/BX receive
Data Sheet
100 Mbit/s(on) or 10 Mbit/s(off)
Link (Keeps on when link ok) or Activity (Blink with 10 Hz when receiving or transmitting but not collision)
FD (Keeps on when in Full duplex mode) or Collision (Blink with 20 Hz when colliding)
100 Link (On when 100M link ok)
10 Link (On when 10M link ok)
Activity (Blink with 10 Hz when receiving or transmitting)
FD (Keeps on when in Full duplex mode) or Collision (Blink with 20 Hz when colliding)
Valid destination address that can pass the address filter of the AN983B/BX
The payload of frame must include at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of IEEE
address.
The frame can contain multiple ‘six FF + sixteen IEEE address’ pattern.
CRC OK
LED Display Operation
First Mode – 3 LED Displays
Second Mode – 4 LED Displays
Reset Operation
Reset Whole Chip
Reset Transceiver Only
Wake on LAN Function
The Magic Packet Format
The Wake on LAN Operation
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Functional Descriptions
Rev. 1.81, 2005-12-15
AN983B/BX