AN983BLX-BG-T-V1 Infineon Technologies, AN983BLX-BG-T-V1 Datasheet - Page 59

• Manufacturer Part Number: AN983BLX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-FQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BLX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BLXBGTV1; SP000076446

Field
GPTT
Res
RWT
RPS
RDU
RCI
TUF
Res
TJT
TDU
TPS
Data Sheet
Bits
11
10
9
8
7
6
5
4
3
2
1
Type
ro/lh
ro
ro/lh
ro/lh
ro/lh
ro/lh
ro/lh
ro
ro/lh
ro/lh
ro/lh
Description
General Purpose Timer Time-out
Base on CSR11 timer register.
Note: lh: High Latching and cleared by writing 1
Reserved
Receive Watchdog Time-out
Based on CSR15 watchdog timer register.
Note: lh: High Latching and cleared by writing 1
Receive Process Stopped
Receive state = stop
Note: lh: High Latching and cleared by writing 1
Receive Descriptor Unavailable
Note: lh: High Latching and cleared by writing 1
1
Receive Completed Interrupt
Note: lh: High Latching and cleared by writing 1
1
Transmit Under-Flow
Note: lh: High Latching and cleared by writing 1
1
Reserved
Transmit Jabber Timer Time-out
Note: lh: High Latching and cleared by writing 1
1
Transmit Descriptor Unavailable
Note: lh: High Latching and cleared by writing 1
1
Transmit Process Stopped
Note: lh: High Latching and cleared by writing 1
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
The receive process is suspended in this situation. To restart the
receive process the ownership bit of next receive descriptor should
be set to AN983B/BX and a receive poll demand command should
be issued (or a new recognized frame is received, if the receive poll
demand is not issued).
during transmitting. The transmit process will enter the suspended
state and report the under-flow error on bit1 of TDES0
will enter the stop state and the transmit jabber time-out flag of bit
14 of TDES0 will be asserted
The transmission process is suspended in this situation. To restart
the transmission process the ownership bit of next transmit
descriptor should be set to AN983B/BX and if the transmit
automatic polling is not enabled then a transmit poll demand
command should be issued.
, while the next receive descriptor can’t be applied by AN983B/BX.
, while the next transmit descriptor can’t be applied by AN983B/BX.
, while a frame reception is completed
, while the transmit FIFO had an under-flow condition happened
, while the transmit jabber timer expired. The transmit processor
, while transmit state = stop
59
Rev. 1.81, 2005-12-15
AN983B/BX