P87LPC767BN NXP Semiconductors, P87LPC767BN Datasheet - Page 49

• Manufacturer Part Number: P87LPC767BN
• Description: MCU 8-Bit 87LP 80C51 CISC 4KB EPROM 3.3V/5V 20-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC767BN

• Package: 20PDIP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• On-chip Adc: 4-chx8-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
Additional Features
The AUXR1 register contains several special purpose control bits that
relate to several chip features. AUXR1 is described in Figure 37.
Software Reset
The SRST bit in AUXR1 allows software the opportunity to reset the
processor completely, as if an external reset or watchdog reset had
occurred. If a value is written to AUXR1 that contains a 1 at bit
position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to
AUXR1 to avoid accidental software resets.
Dual Data Pointers
The dual Data Pointer (DPTR) adds to the ways in which the
processor can specify the address used with certain instructions.
The DPS bit in the AUXR1 register selects one of the two Data
Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
2002 Mar 25
INC
JMP
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
AUXR1
DPTR
@A+DPTR
BIT
AUXR1.7
AUXR1.6
AUXR1.5
AUXR1.4
AUXR1.3
AUXR1.2
AUXR1.1
AUXR1.0
Address: A2h
Not Bit Addressable
SYMBOL
SRST
LPEP
BOD
DPS
KBF
BOI
Increments the Data Pointer by 1.
Jump indirect relative to DPTR value.
—
—
KBF
7
FUNCTION
Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt
function goes low. Must be cleared by software.
Brown Out Disable. When set, turns off brownout detection and saves power. See Power
Monitoring Functions section for details.
Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows
the brownout detect function to be used as an interrupt. See the Power Monitoring Functions
section for details.
Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can
only be cleared by power-on or brownout reset. See the Power Reduction Modes section for
details.
Software Reset. When set by software, resets the P87LPC767 as if a hardware reset occurred.
This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without
interfering with other bits in the register.
Reserved for future use. Should not be set to 1 by user programs.
Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details.
BOD
6
BOI
5
Figure 37. AUXR1 Register
LPEP
4
46
Also, any instruction that reads or manipulates the DPH and DPL
registers (the upper and lower bytes of the current DPTR) will be
affected by the setting of DPS. The MOVX instructions have limited
application for the P87LPC767 since the part does not have an
external data bus. However, they may be used to access EPROM
configuration information (see EPROM Characteristics section).
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the
DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of
inadvertently altering other bits in the register.
SRST
MOV
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
3
DPTR, #data16
2
0
—
1
Load the Data Pointer with a 16-bit
constant.
Move code byte relative to DPTR to the
accumulator.
Move data byte the accumulator to data
memory relative to DPTR.
Move data byte from data memory
relative to DPTR to the accumulator.
DPS
0
P87LPC767
Reset Value: 00h
SU01639
Product data