ISL97671AIRZ-T Intersil, ISL97671AIRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL97671AIRZ-T
• Description: IC LED DRVR 6-CH BACKLIGHT 20QFN
• Manufacturer: Intersil
• Series: -r

Specifications of ISL97671AIRZ-T

• Constant Current: -
• Constant Voltage: -
• Topology: PWM, Step-Up (Boost)
• Number Of Outputs: 6
• Internal Driver: Yes
• Type - Primary: Automotive, Backlight
• Type - Secondary: RGB
• Frequency: 475kHz ~ 640kHz, 970kHz ~ 1.31MHz
• Voltage - Supply: 4.5 V ~ 26.5 V
• Voltage - Output: 45V
• Mounting Type: Surface Mount
• Package / Case: 20-VFQFN Exposed Pad
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: ISL97671AIRZ-TTR

Device Control Register (0x01)
This register has two bits that control either SMBus/I
controlled or external PWM controlled PWM dimming and a
single bit that controls the BL ON/OFF state. The remaining bits
are reserved. The bit assignment is shown in Figure 31. All other
bits in the Device Control Register will read as low unless
otherwise written.
• All reserved bits have no functional effect when written.
• All defined control bits return their current, latched value when
A value of 1 written to BL_CTL turns on the BL in 4ms or less after
the write cycle completes. The BL is
• deemed to be on when Bit 3 BL_STAT of Register 0x02 is 1 and
• A value of 0 written to BL_CTL immediately turns off the BL. The BL
• When SMBus/I
The default value for Register 0x01 is 0x00.
Bit 7 (R/W)
read.
Register 0x09 is not 0.
is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 and
Register 0x09 is 0.
reflects the last value written to it from SMBus/I
Bit 7 (R/W)
RESERVED
PWM_MD
REGISTER 0x00
BRT7
REGISTER 0x01
BIT ASSIGNMENT
X
0
0
1
1
BRT[7..0]
Bit 6 (R/W)
Bit 6 (R/W)
RESERVED
2
BRT6
C mode with DPST is selected, Register 0x00
PWM_SEL
X
0
1
0
1
PWM BRIGHTNESS CONTROL REGISTER
Bit 5 (R/W)
20
DEVICE CONTROL REGISTER
= 256 steps of PWM brightness levels
BRT5
Bit 5 (R/W)
RESERVED
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
BL_CTL
0
1
1
1
1
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
Bit 4 (R/W)
BIT FIELD DEFINITIONS
BRT4
Bit 4 (R/W)
RESERVED
Backlight Off
SMBus/I
PWMI controlled PWM dimming
SMBus/I
SMBus/I
2
C.
2
C
Bit 3 (R/W)
2
2
2
ISL97671A
C and PWM dimming (DPST)
C controlled PWM dimming
C controlled PWM dimming
BRT3
Bit 3 (R/W)
RESERVED
Bit 2 (R/W)
MODE
The PWM_SEL bit determines whether the SMBus/I
input should drive the output brightness in terms of PWM
dimming. When PWM_SEL bit is 1, the PWM drives the output
brightness regardless of what the PWM_MD is.
When the PWM_SEL bit is 0, the PWM_MD bit selects the
manner in which the PWM dimming is to be interpreted; when
this bit is 1, the PWM dimming is based on the SMBus/I
brightness setting. When this bit is 0, the PWM dimming reflects
a percentage change in the current brightness programmed in
the SMBus/I
Technology) mode as:
Where:
Cbt = Current brightness setting from SMBus/I
without influence from the PWM
DSPT Brightness
BRT2
PWM_MD
TABLE 4. OPERATING MODES SELECTED BY DEVICE CONTROL
Bit 2 (R/W)
PWM_MD
X
1
0
Bit 1 (R/W)
2
REGISTER BITS 1 AND 2
C Register 0x00, i.e. DPST (Display Power Saving
PWM_SEL
BRT1
1
0
0
Bit 1 (R/W)
=
PWM_SEL
Cbt
×
PWM Mode
SMBus/I
SMBus/I
Bit 0 (R/W)
PWM
BRT0
Bit 0 (R/W)
BL_CTL
2
2
C Mode
C and PWM Mode with DPST
MODE
2
C Register 0x00
2
C or PWM
March 24, 2011
2
C
FN7709.1
(EQ. 16)