TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 152

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
1. A multiframe is 16 or 64 frames, depending on the TTI format.
11.20 PERFORMANCE COUNTERS
11.19.2 TTI Mismatch Process
11.19.3 TTI Report Process
11.20.1 SDH/SONET Related Performance Counters
The TTI framer frames on TFAS or CR/LF. The framer freewheels when not locked to allow
mismatch detection when expecting a repeating specific byte.
The TIM defect is set when the received TTI does not match the format or value of the
expected TTI during a configurable number of consecutive multiframes
cleared when the received TTI has the same format and value as the expected TTI during a
configurable number of consecutive multiframes.
In case of repeating non-specific byte mode, the defined expected value will be ignored.
Comparisons are made with the previous samples.
The received TTI value is accepted when 3 subsequent identical 16 respectively 64 byte
multiframes are received. Note that when both 16-byte and 64-byte trace message modes
are supported as is the case for path overhead monitoring (J1), the received 16-byte trace
message is only accepted when 4 subsequent identical 16 byte multiframes are received.
This condition when the received TTI equals the accepted TTI is indicated as stable.
If the new multiframe TTI message is the same as the previously accepted message, only 1
multiframe is required to assert the Stable_1 indication. For the Stable_64 indication, 3
multiframes are needed and for the Stable_16 indication, 3 multiframes are needed in case
no 64-byte trace message mode is supported, otherwise 4 multiframes are needed.
Latched registers are provided for the Stable indications. This guarantees consistency when
the reported TTI message is being read out by software:
Note 1: Stable_1 is the inverse of TIM1
Note 2: Stable_16 will inhibit Stable_64
Note 3: Stable_16 will also indicate stable one byte messages. In this case software has to
The PHAST-12P supports the following SDH/SONET related performance counters:
• RS/section counters per line interface:
1. Clear the Stable indication latch (clear-on-write-1).
2. Read out the reported TTI message.
3. The Stable indication latch must still be deasserted. If not, the stable indication (and
• B1 error count, configurable to count either BIP errors or errored frames
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High Order Pointer Tracking, Retiming and Pointer Generation
the reported message) may have changed during software read accesses.
compare the reported message bytes.
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1
. The TIM defect is
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