TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 22

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
4.1 LINE SIDE
4.2 APS PORT SIDE
The PHAST-12P can terminate four individual STM-1/OC-3 lines or a single STM-4/OC-12
line. Each incoming line signal is monitored for loss of signal and clock and data recovery is
performed. Reference clocks derived from each recovered clock are available.
The subsequent TOH Monitor will terminate all RS/section and MS/line overhead bytes
compliant to the latest ITU/ETSI/ANSI standards. Additionally, the received raw TOH
overhead bytes are stored in on-chip memory and output on the TOH port interface for
external processing (except for BIP where the error mask is calculated). The received data
communication channel bytes, selectable RS/section or MS/line, are output on a DCC port
interface per line interface. The K1/K2 APS signal bytes are debounced and forwarded to the
APS interface. RDI and REI are output on the external and internal line ring port interfaces for
ring applications.
The PHAST-12P performs high order pointer processing on the H1/H2 bytes from the receive
line interfaces. The high order path containers are retimed to the local system clock.
High order POH monitoring is performed on all received high order path containers for SNC/P
and UPSR applications.
In the transmit direction, the TOH Generator will insert all RS/section and MS/line overhead
bytes. The TOH overhead bytes can be inserted from on-chip memory or the TOH port
interface. Additionally the data communication channel bytes, selectable RS/section or MS/
line, can be inserted from a DCC port interface. Remote information, RDI and REI can be
inserted from the internal or external ring port interface. This selection can be made on a per
line basis. The K1/K2 APS can be inserted from the APS port interface.
Finally, four individual STM-1/OC-3 lines or a single STM-4/OC-12 line are transmitted using
the device’s system clock.
The serial 622.08 Mbit/s APS port interface is monitored for loss of clock and data recovery is
performed. A reference clock derived from the recovered clock is available.
The received APS port signal is monitored for signal quality and the APS information
exchanged between two mate PHAST-12P devices, including K1/K2 APS signal, signal fail
and signal degrade status, is stored for software access.
The PHAST-12P performs high order pointer processing on the H1/H2 bytes from the receive
APS port. The high order path containers are retimed to the local system clock.
High order POH monitoring is performed on all received high order path containers for SNC/P
and UPSR applications.
4.0 B
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Block Diagram Description
LOCK
D
IAGRAM
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D
ESCRIPTION
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