TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 168

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
Offset
0x001C 0
0x002C 0
0x001A 15 - 0
0x001E 15 - 0
0x0000
0x0010 0
0x0012 0
0x0014 0
0x0016 8 - 0
0x0018 0
0x0020 15 - 0
0x0024 15 - 0
0x0028 0
0x0030 3 - 0
12.2 GLOBAL CONTROL
Bits
DeviceIdentification
STM4_Mode
Reserved
UTOPIA2
TimeOutCount
AckOnTimeOut
LastAddress
Reserved
LocDivider
LocEntryThreshold
LocExitThreshold
External1secRef_Select
DeviceInitialized
GP_Input
Name
Table 2: Global Control
-
Memory Maps and Bit Descriptions
Init
0x1FF rw
0x20 rw
0x0 rw
0x1 rw
0x1 rw
0x1 rw
0x0 ro
0x0 ro
0x4 rw
0x2 rw
0x0 rw
0x0 rw
0x0 ro
ro
(T_GLOBAL_CONTROL)
Access
T_DeviceIdentification
Device identification.
STM-4/OC-12 Mode when 0x1: Line 1 is a 622.08
Mbit/s signal, lines 2 to 4 are not used. STM-1/OC-3
Mode when 0x0: lines 1 to 4 are 155.52 Mbit/s
signals.
Reserved. This field must be set to 0x0.
The terminal interface operates in POS-PHY Level 2
Mode when 0x0. The terminal interface operates in
UTOPIA Level 2 mode when 0x1.
Range 0 to 511
Acknowledge Time Out Count. Specifies the Time
Out after which an Acknowledge is generated if a
request hasn’t been acknowledged. Timebase is the
microprocessor clock period (MPCLK).
Acknowledge on Time Out. An Acknowledge will be
generated upon failed accesses after a period
specified by TimeOutCount when 0x1. No
Acknowledge will be generated upon failed accesses
when 0x0.
Last Address. Indicates the address of the last timed-
out request.
Note: The address returned is a word address.
Reserved.
Range 0 to 65535
Loss Of Clock Divider. The clock to be monitored is
divided by this number + 1 for LOC detection.
Range 1 to 65535
Loss Of Clock Entry Threshold. Specifies the time
without divided clock transition before declaring LOC.
Timebase is the microprocessor clock period
(MPCLK).
Range 1 to 65535
Loss Of Clock Exit Threshold. LOC is deasserted
when this many divided clock transitions were
detected. Detection occurs in the microprocessor
clock domain (MPCLK).
External One Second Reference Select.
The one second reference on the REFONESECCLK
is used when 0x1. The one second reference is
generated internally when 0x0.
The device processes incoming data when this value
is set to 0x1. The software must set this value to 0x1
as soon as it has finished the configuration of the
device.
General purpose input (GPIN4..GPIN1).
-
Description
(See page
169.)
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