M69030 Asiliant Technologies, M69030 Datasheet - Page 89

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Chapter 8
General Control and Status Registers
Introduction
Chapter 8 describes the General Control and Status Registers for the 69030 Dual HiQVideo Accelerator.
These are direct-access registers. They are NOT read from or written to using any form of sub-indexing
scheme.
Table 8-1:
Various bits in these registers have bits that provide control over the real-time status of the horizontal sync
signal, the horizontal retrace interval, the vertical sync signal, and the vertical retrace interval.
The horizontal retrace interval is the time when the drawing of each horizontal line has active video data,
when the active video data is not being displayed. It is the time that includes the horizontal front and back
porches, and the horizontal sync pulse. The horizontal retrace interval is always longer than the horizontal
sync pulse.
The vertical retrace interval is the period during the drawing of each screen, when the horizontal lines with
active video data are not drawn. This period includes the vertical front and back porches, and the vertical
sync pulse. The vertical retrace interval is always longer than the vertical sync pulse.
The ‘Display Enable’ status bit (bit 0) in Input Status Register 1 indicates that either a horizontal retrace
interval or a vertical retrace interval is in progress (the name ‘Display Enable’ is misleading for this status
bit because the bit does not enable nor disable the graphics system as it’s name suggests). In the IBM
EGA graphics system (and the ones that preceded it, including MDA and CGA) it was important to check
the status of this bit to ensure that one or the other of the retrace intervals was taking place before accessing
the graphics memory. In these earlier systems reading from or writing to graphics memory outside the
retrace intervals meant that the CRT controller would be cut off from accessing the graphics memory in
order to draw pixels to the display, resulting in either “snow” or a flickering display.
`efmp
Name
ST00
ST01
IOSS
MSR
FCR
MSS

69030 Databook
General Control and Status Registers
Memory Shadowing Register (shared)
I/O Space Shadowing Register (shared)
Input Status Register 0
Input Status Register 1
Feature Control Register
Miscellaneous Output Register
General Control and Status Registers
Function
3BAh/3DAh
Read
3CAh
3CCh
3CDh
3CBh
3C2h
Revision 1.3 11/24/99
3BAh/3DAh
Write
3CDh
3CBh
3C2h
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8-1