M69030 Asiliant Technologies, M69030 Datasheet - Page 96

• Manufacturer Part Number: M69030
• Manufacturer: Asiliant Technologies

Specifications of M69030

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-8
4
3
`efmp

Sub-indexed Register Index Write Enable
Sub-indexed Register Index A/B Select
69030 Databook
This bit defaults to the value of 0 after reset.
For the FCR, MSR, MSS, ST00 and ST01 registers:
For the CR sub-indexed register group:
For the FR, GR, MR, SR and XR sub-indexed register groups:
For the AR and DAC register groups:
This bit defaults to the value of 0 after reset.
For the FCR, MSR, MSS, ST00 and ST01 registers:
For the CR sub-indexed register group:
For the FR, GR, MR, SR and XR sub-indexed register groups:
For the AR and DAC register groups:
Since these are direct-access and not sub-indexed registers, this bit has no effect
on these registers.
This bit has no effect on write accesses from the I/O space to the index of this sub-
indexed register group on either pipeline. Instead, bits 1 and 0 of this register
control write access to one or both shadows of the index along with write accesses
to the actual sub-indexed registers.
0: Disables write accesses (read access is always enabled) from the I/O space to
the indices of these sub-indexed register groups regardless of whichever pipeline
is selected by bit 3 of this register.
1: Enables write accesses from the I/O space to the indices of these sub-indexed
register groups of whichever pipeline is selected by bit 3 of this register.
This bit has no effect on write accesses from the I/O space to the indices of these
sub-indexed register groups of either pipeline. Instead, bits 1 and 0 of this register
control write access to one or both shadows of these indices along with write
accesses to the actual sub-indexed registers.
Since these are direct-access and not sub-indexed registers, this bit has no effect
on these registers.
This bit has no effect on the selection of which pipeline’s index for this sub-indexed
register group is used in making accesses to the actual sub-indexed registers. In-
stead, bits 2 through 0 select both which pipeline’s set of these sub-indexed regis-
ters and index will be made accessible for read or write accesses.
0: Selects pipeline A’s indices for these sub-indexed register groups to be used in
making accesses to these sub-indexed registers from the I/O space, regardless of
whether the actual sub-indexed registers being accessed belong to pipeline A or
B, or are shared.
1: Selects pipeline B’s indices for these sub-indexed register groups to be used in
making accesses to these sub-indexed registers from the I/O space, regardless of
whether the actual sub-indexed registers being accessed belong to pipeline A or
B, or are shared.
This bit has no effect on the selection of which pipeline’s indices for these sub-in-
dexed register groups are used in making accesses to the actual sub-indexed reg-
isters. Instead, bits 2 through 0 select both which pipeline’s sets of these sub-
indexed registers and their indices will be made accessible for read or write ac-
cesses.
General Control and Status Registers
Revision 1.3 11/24/99